gem5
Class List
Here are the classes, structs, unions and interfaces with brief descriptions:
[detail level 12345]
 NAlphaISA
 NArmISA
 NBitfieldBackend
 NBrig
 NCopyEngineReg
 Ncp
 NDebug
 NDecodeCache
 NFreeBSD
 NGenericISA
 NHsailISA
 NiGbReg
 NKernel
 NLinux
 Nm5
 NMinorMinor contains all the definitions within the MinorCPU apart from the CPU class itself
 NMipsISA
 NNet
 NNullISA
 NPowerISA
 NProbePointsName space containing shared probe point declarations
 NPs2
 NPseudoInst
 NRiscvISA
 NSimClockThese are variables that are set based on the simulator frequency
 NSinic
 NSparcISA
 NStats
 NstdOverload hash function for BasicBlockRange type
 NTheISA
 NTrace
 NX86ISAThis is exposed globally, independent of the ISA
 NX86ISAInst
 C_cl_event
 CA9GlobalTimer
 CA9SCU
 CAbstractBloomFilter
 CAbstractCacheEntry
 CAbstractController
 CAbstractEntry
 CAbstractMemoryAn abstract memory represents a contiguous block of physical memory, with an associated address range, and also provides basic functionality for reading and writing this memory without any timing information
 CAbstractNVMThis is an interface between the disk interface (which will handle the disk data transactions) and the timing model
 CAbstractReplacementPolicy
 CAccessTraceForAddress
 CActivityRecorderActivityRecorder helper class that informs the CPU if it can switch over to being idle or not
 CAddressProfiler
 CAddrMapperAn address mapper changes the packet addresses in going from the slave port side of the mapper to the master port side
 CAddrOperandBase
 CAddrRangeEncapsulates an address range, and supports a number of tests to check if two ranges intersect, if a range contains a specific address etc
 CAddrRangeMapThe AddrRangeMap uses an STL map to implement an interval tree for address decoding
 CAlphaAccess
 CAlphaBackdoorMemory mapped interface to the system console
 CAlphaLinux
 CAlphaProcess
 CAlphaSystem
 CAmbaDevice
 CAmbaDmaDevice
 CAmbaFake
 CAmbaIntDevice
 CAmbaPioDevice
 CAnnotateDumpCallback
 Caout_exechdrFunky Alpha 64-bit a.out header used for PAL code
 CAoutObject
 CArchTimerPer-CPU architected timer
 CArchTimerKvm
 CArguments
 CArmFreebsd32
 CArmFreebsd64
 CArmFreebsdProcess32A process with emulated Arm/Freebsd syscalls
 CArmFreebsdProcess64A process with emulated Arm/Freebsd syscalls
 CArmFreebsdProcessBits
 CArmKvmCPUARM implementation of a KVM-based hardware virtualized CPU
 CArmLinux32
 CArmLinux64
 CArmLinuxProcess32A process with emulated Arm/Linux syscalls
 CArmLinuxProcess64A process with emulated Arm/Linux syscalls
 CArmLinuxProcessBits
 CArmProcess
 CArmProcess32
 CArmProcess64
 CArmSemihostingSemihosting for AArch32 and AArch64
 CArmSystem
 CArmV8KvmCPUThis is an implementation of a KVM-based ARMv8-compatible CPU
 CAtagCmdline
 CAtagCore
 CAtagHeader
 CAtagMem
 CAtagNone
 CAtagRev
 CAtagSerial
 Cataparams
 CAtomicOpAdd
 CAtomicOpAnd
 CAtomicOpCAS
 CAtomicOpDec
 CAtomicOpExch
 CAtomicOpFunctor
 CAtomicOpInc
 CAtomicOpMax
 CAtomicOpMin
 CAtomicOpOr
 CAtomicOpSub
 CAtomicOpXor
 CAtomicSimpleCPU
 CAUXU
 CAuxVector
 CBackingStoreEntryA single entry for the backing store
 CBadDeviceBadDevice This device just panics when accessed
 CBankedArray
 CBareIronMipsSystemThis class contains linux specific system code (Loading, Events)
 CBarrier
 CBaseArmKvmCPU
 CBaseBufferArgBase class for BufferArg and TypedBufferArg, Not intended to be used directly
 CBaseCacheA basic cache interface
 CBaseCPU
 CBaseDynInst
 CBaseGdbRegCacheConcrete subclasses of this abstract class represent how the register values are transmitted on the wire
 CBaseGenBase class for all generators, with the shared functionality and virtual functions for entering, executing and leaving the generator
 CBaseGic
 CBaseGicRegisters
 CBaseGlobalEventCommon base class for GlobalEvent and GlobalSyncEvent
 CBaseGlobalEventTemplateFunky intermediate class to support CRTP so that we can have a common constructor to create the local events, even though the types of the local events are defined in the derived classes
 CBaseKvmCPUBase class for KVM based CPU models
 CBaseKvmTimerTimer functions to interrupt VM execution after a number of simulation ticks
 CBaseMasterPortA BaseMasterPort is a protocol-agnostic master port, responsible only for the structural connection to a slave port
 CBaseMemProbeBase class for memory system probes accepting Packet instances
 CBaseO3CPU
 CBaseO3DynInst
 CBaseOperand
 CBasePixelPumpTiming generator for a pixel-based display
 CBasePrefetcher
 CBaseRegOperand
 CBaseRemoteGDB
 CBaseReplacementPolicyA common base class of cache replacement policy objects
 CBaseSetAssocA BaseSetAssoc cache tag store
 CBaseSimpleCPU
 CBaseSlavePortA BaseSlavePort is a protocol-agnostic slave port, responsible only for the structural connection to a master port
 CBaseTagsA common base class of Cache tagstore objects
 CBaseTagsCallback
 CBaseTagsDumpCallback
 CBaseTLB
 CBaseXBarThe base crossbar contains the common elements of the non-coherent and coherent crossbar
 CBasicBlock
 CBasicExtLink
 CBasicIntLink
 CBasicLink
 CBasicPioDevice
 CBasicRouter
 CBasicSignal
 CBiModeBPImplements a bi-mode branch predictor
 CBIPRP
 CBitfieldROType
 CBitfieldType
 CBitfieldTypeImpl
 CBitfieldWOType
 CBitUnionData
 CBlockBloomFilter
 CBmpWriter
 CBPredUnitBasically a wrapper class to hold both the branch predictor and the BTB
 CBreakPCEvent
 CBridgeA bridge is used to interface two different crossbars (or in general a memory-mapped master and slave), with buffering for requests and responses
 CBrigObject
 CBrigRegOperandInfo
 CBRRIPRP
 CBufferArgBufferArg represents an untyped buffer in target user space that is passed by reference to an (emulated) system call
 CBulkBloomFilter
 CCacheA template-policy based cache
 CCacheBlkA Basic Cache block
 CCacheBlkIsDirtyVisitorCache block visitor that determines if there are dirty blocks in a cache
 CCacheBlkPrintWrapperSimple class to provide virtual print() method on cache blocks without allocating a vtable pointer for every single cache block
 CCacheBlkVisitorBase class for cache block visitor, operating on the cache block base class (later subclassed for the various tag classes)
 CCacheBlkVisitorWrapperWrap a method and present it as a cache block visitor
 CCacheMemory
 CCacheRecorder
 CCacheSetAn associative set of cache blocks
 CCallArgMem
 CCallbackGeneric callback class
 CCallbackQueue
 CCheck
 CCheckerTemplated Checker class
 CCheckerCPUCheckerCPU class
 CCheckerThreadContextDerived ThreadContext class for use with the Checker
 CCheckpointIn
 CCheckTable
 CChunkGeneratorThis class takes an arbitrary memory region (address/length pair) and generates a series of appropriately (e.g
 CCircleBufCircular buffer backed by a vector
 CClDriver
 CClockDomainThe ClockDomain provides clock to group of clocked objects bundled under the same clock domain
 CClockedHelper class for objects that need to be clocked
 CClockedObjectExtends the SimObject with a clock and accessor functions to relate ticks to the cycles of the object
 CClockedObjectDumpCallback
 CCoherentXBarA coherent crossbar connects a number of (potentially) snooping masters and slaves, and routes the request and response packets based on the address, and also forwards all requests to the snoopers and deals with the snoop responses
 CCommandReg
 CCommMonitorThe communication monitor is a MemObject which can monitor statistics of the communication happening between two ports in the memory system
 CComputeUnit
 CConditionRegisterState
 CConsumer
 CControlFlowInfo
 CCopyEngine
 CCountedExitEvent
 CCowDiskCallback
 CCowDiskImageSpecialization for accessing a copy-on-write disk image layer
 CCPA
 CCPAIgnoreSymbol
 CCpuEventThis class creates a global list of events that need a pointer to a thread context
 CCpuEventWrapper
 CCpuLocalTimer
 CCredit
 CCreditLink
 CCRegOperand
 CCrossbarSwitch
 CCustomNoMaliGpu
 CCxxConfigDirectoryEntryConfig details entry for a SimObject
 CCxxConfigFileBaseConfig file wrapper providing a common interface to CxxConfigManager
 CCxxConfigManagerThis class allows a config file to be read into gem5 (generating the appropriate SimObjects) from C++
 CCxxConfigParamsBase for peer classes of SimObjectParams derived classes with parameter modifying member functions
 CCxxIniFileCxxConfigManager interface for using .ini files
 CCyclesCycles is a wrapper class for representing cycle counts, i.e
 CDataBlock
 CDataTranslationThis class represents part of a data address translation
 CDebugBreakEvent
 CDecoderFaultInst
 CDefaultBTB
 CDefaultCommitDefaultCommit handles single threaded and SMT commit
 CDefaultDecodeDefaultDecode class handles both single threaded and SMT decode
 CDefaultDecodeDefaultRenameStruct that defines the information passed from decode to rename
 CDefaultFetchDefaultFetch class handles both single threaded and SMT fetch
 CDefaultFetchDefaultDecodeStruct that defines the information passed from fetch to decode
 CDefaultIEWDefaultIEW handles both single threaded and SMT IEW (issue/execute/writeback)
 CDefaultIEWDefaultCommitStruct that defines the information passed from IEW to commit
 CDefaultRenameDefaultRename handles both single threaded and SMT rename
 CDefaultRenameDefaultIEWStruct that defines the information passed from rename to IEW
 CDependencyEntryNode in a linked list
 CDependencyGraphArray of linked list that maintains the dependencies between producing instructions and consuming instructions
 CDerivedClockDomainThe derived clock domains provides the notion of a clock domain that is connected to a parent clock domain that can either be a source clock domain or a derived clock domain
 CDerivO3CPU
 CDeviceFDEntryHolds file descriptors needed to simulate devices opened with pseudo files (commonly with calls to ioctls)
 CDirectedGenerator
 CDirectoryMemory
 CDiskImageBasic interface for accessing a disk image
 CDisplayTimings
 CDistEtherLinkModel for a fixed bandwidth full duplex ethernet link
 CDistHeaderPkt
 CDistIfaceThe interface class to talk to peer gem5 processes
 CDmaCallbackDMA callback class
 CDmaDevice
 CDmaPort
 CDmaReadFifoBuffered DMA engine helper class
 CDMARequest
 CDMASequencer
 CDmesgEntry
 CDNR
 Cdp_regsEthernet device registers
 Cdp_rom
 CDrainableInterface for objects that might require draining before checkpointing
 CDrainManagerThis class coordinates draining of a System
 CDRAMCtrlThe DRAM controller is a single-channel memory controller capturing the most important timing constraints associated with a contemporary DRAM
 CDramGenDRAM specific generator is for issuing request with variable page hit length and bank utilization
 CDRAMPowerDRAMPower is a standalone tool which calculates the power consumed by a DRAM in the system
 CDramRotGen
 CDRAMSim2
 CDRAMSim2WrapperWrapper class to avoid having DRAMSim2 names like ClockDomain etc clashing with the normal gem5 world
 CDRegOperand
 CDtbObject
 CDumbTODDumbTOD simply returns some idea of time when read
 CDummyCheckerSpecific non-templated derived class used for SimObject configuration
 CDumpStatsPCEvent
 CDumpStatsPCEvent64
 CDVFSHandlerDVFS Handler class, maintains a list of all the domains it can handle
 Cecoff_aouthdr
 Cecoff_exechdr
 Cecoff_extsym
 Cecoff_fdr
 Cecoff_filehdr
 Cecoff_scnhdr
 Cecoff_sym
 Cecoff_symhdr
 CEcoffObject
 CElasticTraceThe elastic trace is a type of probe listener and listens to probe points in multiple stages of the O3CPU
 CElfObject
 CEmbeddedPyBind
 CEmbeddedPython
 CEmulatedDriverEmulatedDriver is an abstract base class for fake SE-mode device drivers
 CEmulationPageTable
 CEndQuiesceEventEvent for timing out quiesce instruction
 CEnergyCtrl
 CEtherBus
 CEtherDevBaseDummy class to keep the Python class hierarchy in sync with the C++ object hierarchy
 CEtherDeviceThe base EtherObject class, allows for an accesor function to a simobj that returns the Port
 CEtherDump
 CEtherInt
 CEtherLink
 CEtherObjectThe base EtherObject class, allows for an accesor function to a simobj that returns the Port
 CEtherSwitch
 CEtherTapBase
 CEtherTapInt
 CEtherTapStub
 CEthPacketData
 CEvent
 CEventBaseCommon base class for Event and GlobalEvent, so they can share flag and priority definitions and accessor functions
 CEventFunctionWrapper
 CEventManager
 CEventQueueQueue of events sorted in time order
 CEventWrapper
 CExecContextThe ExecContext is an abstract base class the provides the interface used by the ISA to manipulate the state of the CPU model
 CExecStage
 CExitGenThe exit generator exits from the simulation once entered
 CExternalMaster
 CExternalSlave
 CFailUnimplementedStatic instruction class for unimplemented instructions that cause simulator termination
 CFALRUA fully associative LRU cache
 CFALRUBlkA fully associative cache block
 CFaultBase
 CFaultModel
 CFDArray
 CFDEntryHolds a single file descriptor mapping and that mapping's data for processes running in syscall emulation mode
 CFetchStage
 CFetchUnit
 CFifoSimple FIFO implementation backed by a circular buffer
 CFIFORP
 CFileFDEntryHolds file descriptors for host-backed files; host-backed files are files which were opened on the physical machine where the simulation is running (probably the thing on/under your desk)
 CFlags
 CFlashDeviceFlash Device model The Flash Device model is a timing model for a NAND flash device
 Cflit
 CflitBuffer
 CFloat16
 CFrameBufferInternal gem5 representation of a frame buffer
 CFreeBSDThis class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Alpha FreeBSD syscall interface
 CFreebsdAlphaSystem
 CFreebsdArmSystem
 CFSTranslatingPortProxyA TranslatingPortProxy in FS mode translates a virtual address to a physical address and then calls the read/write functions of the port
 CFUDesc
 CFullO3CPUFullO3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buffers between stages
 CFunctionProfile
 CFunctionRefOperand
 CFuncUnit
 CFUPoolPool of FU's, specific to the new CPU model
 CFutexKeyFutexKey class defines an unique identifier for a particular futex in the system
 CFutexMapFutexMap class holds a map of all futexes used in the system
 CFXSave
 CGarnetExtLink
 CGarnetIntLink
 CGarnetNetwork
 CGarnetSyntheticTraffic
 CGenericAlignmentFault
 CGenericArmPciHost
 CGenericArmSystem
 CGenericPageTableFault
 CGenericPciHostConfigurable generic PCI host interface
 CGenericTimer
 CGenericTimerISA
 CGenericTimerMem
 CGenericTLB
 CGicv2m
 CGicv2mFrameUltimately this class should be embedded in the Gicv2m class, but this confuses Python as 'Gicv2m::Frame' gets interpreted as 'Frame' in namespace Gicv2m
 CGlobalEventThe main global event class
 CGlobalMemPipeline
 CGlobalsContainer for serializing global variables (not associated with any serialized object)
 CGlobalSimLoopExitEvent
 CGlobalSyncEventA special global event that synchronizes all threads and forces them to process asynchronously enqueued events
 CGoodbyeObject
 CGPUCoalescer
 CGPUCoalescerRequest
 CGpuDispatcher
 CGPUDynInst
 CGPUExecContext
 CGPUStaticInst
 CH3BloomFilter
 CHardBreakpoint
 CHBFDEntryExtends the base class to include a host-backed file descriptor field that records the integer used to represent the file descriptor on the host and the file's flags
 CHDLcd
 CHelloObject
 CHexFile
 CHistogram
 CHMCControllerHMC Controller, in general, is responsible for translating the host protocol (AXI for example) to serial links protocol
 CHostState
 CHsaCode
 CHsaDriverSizes
 CHsailCode
 CHsaKernelInfo
 CHsaObject
 CHsaQueueEntry
 CI2CBus
 CI2CDevice
 CIdeControllerDevice model for an Intel PIIX4 IDE controller
 CIdeDiskIDE Disk device model
 CIdleGenThe idle generator does nothing
 CIdleStartEvent
 CIGbE
 CIGbEInt
 CImgWriter
 CImmOp
 CImmOp64
 CImmOperand
 CIndirectPredictor
 CIniFileThis class represents the contents of a ".ini" file
 CinitRenameModeHelper structure to get the vector register mode for a given ISA
 CinitRenameMode< ArmISA::ISA >
 CInputUnit
 CInstResult
 CInstructionQueueA standard instruction queue class
 CIntel8254TimerProgrammable Interval Timer (Intel 8254)
 CIntrControl
 CInvalidateGenerator
 CIob
 CIsaFakeIsaFake is a device that returns, BadAddr, 1 or 0 on all reads and rites
 CIssueStruct
 CKernelLaunchStaticInst
 CKvmKVM parent interface
 CKvmDeviceKVM device wrapper
 CKvmFPReg
 CKvmKernelGicV2KVM in-kernel GIC abstraction
 CKvmVMKVM VM container
 CLabel
 CLabelMap
 CLabelOperand
 CLaneDataLaneSize is an abstraction of a LS byte value for the execution and thread contexts to handle values just depending on its width
 CLdsChunkThis represents a slice of the overall LDS, intended to be associated with an individual workgroup
 CLdsState
 CLFURP
 CLinearEquationThis class describes a linear equation with constant coefficients
 CLinearGenThe linear generator generates sequential requests from a start to an end address, with a fixed block size
 CLinearSystem
 CLinkEntry
 CLinkOrder
 CLinuxThis class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Alpha Linux syscall interface
 CLinuxAlphaSystemThis class contains linux specific system code (Loading, Events)
 CLinuxArmSystem
 CLinuxMipsSystemThis class contains linux specific system code (Loading, Events)
 CLinuxX86System
 CListenSocket
 CListOperand
 CLocalBPImplements a local predictor that uses the PC to index into a table of counters
 CLocalMemPipeline
 CLocalSimLoopExitEvent
 CLockedAddrLocked address class that represents a physical address and a context id
 CLogger
 CLRUPolicy
 CLRURP
 CLSB_CountingBloomFilter
 CLSQ
 CLSQUnitClass that implements the actual LQ and SQ for each specific thread
 CLTAGE
 Cltseqnum
 CMachineID
 CMakeCallbackHelper template class to turn a simple class member function into a callback
 CMaltaTop level class for Malta Chipset emulation
 CMaltaCChipMalta CChip CSR Emulation
 CMaltaIOMalta I/O device is a catch all for all the south bridge stuff we care to implement
 CMasterPortA MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the three different level of transport functions
 CMathExpr
 CMathExprPowerModelA Equation power model
 CMC146818Real-Time Clock (MC146818)
 CMcrMrcImplDefinedThis class is also used for IMPLEMENTATION DEFINED registers, whose mcr/mrc behaviour is trappable even for unimplemented registers
 CMcrMrcMiscInstCertain mrc/mcr instructions act as nops or flush the pipe based on what register the instruction is trying to access
 CMcrrOp
 CMemCheckerMemChecker
 CMemCheckerMonitorImplements a MemChecker monitor, to be inserted between two ports
 CMemCmd
 CMemDepUnitMemory dependency unit class
 CMemFootprintProbeProbe to track footprint of accessed memory Two granularity of footprint measurement i.e
 CMemObjectExtends the ClockedObject with accessor functions to get its master and slave ports
 CMemStateThis class holds the memory state for the Process class and all of its derived, architecture-specific children
 CMemTestTests a cache coherent memory system by generating false sharing and verifying the read data against a reference updated on the completion of writes
 CMemTraceProbe
 CMessage
 CMessageBuffer
 CMessageMasterPort
 CMessageSlavePort
 CMicrocodeRom
 CMinorCPUMinorCPU is an in-order CPU model with four fixed pipeline stages:
 CMinorFUA functional unit that can execute any of opClasses operations with a single op(eration)Lat(ency) and issueLat(ency) associated with the unit rather than each operation (as in src/FuncUnit)
 CMinorFUPoolA collection of MinorFUs
 CMinorFUTimingExtra timing capability to allow individual ops to have their source register dependency latencies tweaked based on the ExtMachInst of the source instruction
 CMinorOpClassBoxing for MinorOpClass to get around a build problem with C++11 but also allow for future additions to op class checking
 CMinorOpClassSetWrapper for a matchable set of op classes
 CMipsAccess
 CMipsLinux
 CMipsLinuxProcessA process with emulated Mips/Linux syscalls
 CMipsProcess
 CMipsSystem
 CMiscRegRegImmOp
 CMiscRegRegImmOp64
 CMmDisk
 CMrrcOp
 CMrsOp
 CMRURP
 CMSHRMiss Status and handling Register
 CMSHRQueueA Class for maintaining a list of pending and allocated memory requests
 CMSICAPDefines the MSI Capability register and its associated bitfields for the a PCI/PCIe device
 CMSIXDefines the MSI-X Capability register and its associated bitfields for a PCIe device
 CMSIXCAP
 CMSIXPbaEntry
 CMSIXTable
 CMsrBase
 CMsrImmOp
 CMsrRegOp
 CMultiBitSelBloomFilter
 CMultiGrainBloomFilter
 CMultiLevelPageTable
 CMuxingKvmGic
 CNamed
 CNDRange
 CNetDest
 CNetwork
 CNetworkInterface
 CNetworkLink
 CNoMaliGpu
 CNoncoherentXBarA non-coherent crossbar connects a number of non-snooping masters and slaves, and routes the request and response packets based on the address
 CNonCountingBloomFilter
 CNoRegAddrOperand
 Cns_desc32
 Cns_desc64
 CNSGigENS DP83820 Ethernet device model
 CNSGigEInt
 CO3CheckerSpecific non-templated derived class used for SimObject configuration
 CO3CPUImplImplementation specific struct that defines several key types to the CPU, the stages within the CPU, the time buffers, and the DynInst
 CO3ThreadContextDerived ThreadContext class for use with the O3CPU
 CO3ThreadStateClass that has various thread state, such as the status, the current instruction being processed, whether or not the thread has a trap pending or is being externally updated, the ThreadContext pointer, etc
 CObjectFile
 CObjectMatch
 COFSchedulingPolicy
 COpDesc
 COperatingSystemThis class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to an operating system syscall interface
 COPTR
 COutputDirectoryInterface for creating files in a gem5 output directory
 COutputFile
 COutputStream
 COutputUnit
 COutVcState
 CP9MsgHeader
 CP9MsgInfo
 CPacketA Packet is used to encapsulate a transfer between two objects in the memory system (e.g., the L1 and L2 cache)
 CPacketFifo
 CPacketFifoEntry
 CPacketQueueA packet queue is a class that holds deferred packets and later sends them using the associated slave port or master port
 CPAL
 CPanicPCEvent
 CPc
 Cpcap_file_header
 Cpcap_pkthdr
 CPCEvent
 CPCEventQueue
 CPciBusAddr
 CPCIConfig
 CPciDevicePCI device, base implementation is only config space
 CPciHostThe PCI host describes the interface between PCI devices and a simulated system
 CPciVirtIO
 Cpdr
 CPerfectCacheLineState
 CPerfectCacheMemory
 CPerfectSwitch
 CPerfKvmCounterAn instance of a performance counter
 CPerfKvmCounterConfigPerfEvent counter configuration
 CPerfKvmTimerPerfEvent based timer using the host's CPU cycle counter
 CPersistentTable
 CPersistentTableEntry
 CPhysicalMemoryThe physical memory encapsulates all memories in the system and provides basic functionality for accessing those memories without going through the memory system and interconnect
 CPhysRegFileSimple physical register file class
 CPhysRegIdPhysical register ID
 CPioDeviceThis device is the base class which all devices senstive to an address range inherit from
 CPioPortProgrammed i/o port that all devices that are sensitive to an address range use
 CPipeFDEntryHolds the metadata needed to maintain the mappings for file descriptors allocated with the pipe() system calls and its variants
 CPixelInternal gem5 representation of a Pixel
 CPixelConverterConfigurable RGB pixel converter
 CPl011
 CPL031
 CPl050
 CPl111
 CPl390
 CPlatform
 CPMCAPDefines the Power Management capability register and all its associated bitfields for a PCIe device
 CPngWriterImage writer implementing support for PNG
 CPollEvent
 CPollQueue
 CPoolManager
 CPortPorts are used to interface memory objects to each other
 CPortProxyThis object is a proxy for a structural port, to be used for debug accesses
 CPosixKvmTimerTimer based on standard POSIX timers
 CPowerLinux
 CPowerLinuxProcessA process with emulated PPC/Linux syscalls
 CPowerModel
 CPowerModelStateA PowerModelState is an abstract class used as interface to get power figures out of SimObjects
 CPowerProcess
 CPrdEntry
 CPrdTableEntry
 CPrefetchEntry
 CPrefetcher
 CPrintableAbstract base class for objects which support being printed to a stream for debugging
 CProbeListenerProbeListener base class; here to simplify things like containers containing multiple types of ProbeListener
 CProbeListenerArgProbeListenerArg generates a listener for the class of Arg and the class type T which is the class containing the function that notify will call
 CProbeListenerArgBaseProbeListenerArgBase is used to define the base interface to a ProbeListenerArg (i.e the notify method on specific type)
 CProbeListenerObjectThis class is a minimal wrapper around SimObject
 CProbeManagerProbeManager is a conduit class that lives on each SimObject, and is used to match up probe listeners with probe points
 CProbePointProbeListener base class; again used to simplify use of ProbePoints in containers and used as to define interface for adding removing listeners to the ProbePoint
 CProbePointArgProbePointArg generates a point for the class of Arg
 CProcess
 CProfileNode
 CProfiler
 CProtoInputStreamA ProtoInputStream wraps a coded stream, potentially with decompression, based on looking at the file name
 CProtoOutputStreamA ProtoOutputStream wraps a coded stream, potentially with compression, based on looking at the file name
 CProtoStreamA ProtoStream provides the shared functionality of the input and output streams
 CProxyThreadContextProxyThreadContext class that provides a way to implement a ThreadContext without having to derive from it
 CPS2Device
 CPS2Keyboard
 CPS2Mouse
 CPS2TouchKit
 CPseudoLRUPolicyImplementation of tree-based pseudo-LRU replacement
 CPXCAPDefines the PCI Express capability register and its associated bitfields for a PCIe device
 CPybindSimObjectResolverResolve a SimObject name using the Pybind configuration
 CPyEventPyBind wrapper for Events
 CQueueA high-level queue interface, to be used by both the MSHR queue and the write buffer
 CQueuedMasterPortThe QueuedMasterPort combines two queues, a request queue and a snoop response queue, that both share the same port
 CQueuedPrefetcher
 CQueuedSlavePortA queued port is a port that has an infinite queue for outgoing packets and thus decouples the module that wants to send request/responses from the flow control (retry mechanism) of the port
 CQueueEntryA queue entry base class, to be used by both the MSHRs and write-queue entries
 CRandom
 CRandomGenThe random generator is similar to the linear one, but does not generate sequential addresses
 CRandomRP
 CRangeAddrMapperRange address mapper that maps a set of original ranges to a set of remapped ranges, where a specific range is of the same size (original and remapped), only with an offset
 CRawDiskImageSpecialization for accessing a raw disk image
 CRawObject
 CRealView
 CRealViewCtrl
 CRealViewOscThis is an implementation of a programmable oscillator on the that can be configured through the RealView/Versatile Express configuration interface
 CRealViewTemperatureSensorThis device implements the temperature sensor used in the RealView/Versatile Express platform
 CReconvergenceStackEntryA reconvergence stack entry conveys the necessary state to implement control flow divergence
 CReExec
 CRefCountedDerive from RefCounted if you want to enable reference counting of this class
 CRefCountingPtrIf you want a reference counting pointer to a mutable object, create it like this:
 CRegAddrOperand
 CRegIdRegister ID: describe an architectural register with its class and index
 CRegImmImmOp
 CRegImmOp
 CRegImmRegOp
 CRegImmRegShiftOp
 CRegMiscRegImmOp
 CRegMiscRegImmOp64
 CRegOrImmOperand
 CRegRegImmImmOp
 CRegRegImmImmOp64
 CRegRegImmOp
 CRegRegOp
 CRegRegRegImmOp
 CRegRegRegImmOp64
 CRegRegRegOp
 CRegRegRegRegOp
 CRejectException
 CReqPacketQueue
 CRequest
 CRequestDesc
 CRespPacketQueue
 CReturnAddrStackReturn address stack class, implements a simple RAS
 CRiscvLinux
 CRiscvLinuxProcessA process with emulated Riscv/Linux syscalls
 CRiscvProcess
 CRiscvSystem
 CRNDXR
 CROBROB class
 CRoot
 CRouteInfo
 CRouter
 CRoutingUnit
 CRRSchedulingPolicy
 CRubyDirectedTester
 CRubyPort
 CRubyPortProxy
 CRubyRequest
 CRubyStatsCallback
 CRubySystem
 CRubyTester
 CSatCounterPrivate counter class for the internal saturating counters
 CScheduler
 CScheduleStage
 CSchedulingPolicy
 CScoreboardImplements a simple scoreboard to track which registers are ready
 CScoreboardCheckStage
 CSecurePortProxyThis object is a proxy for a structural port, to be used for debug accesses to secure memory
 CSequencer
 CSequencerRequest
 CSerialDeviceBase class for serial devices such as terminals
 CSerializableBasic support for object serialization
 CSerialLinkSerialLink is a simple variation of the Bridge class, with the ability to account for the latency of packet serialization
 CSerialNullDeviceDummy serial device that discards all data sent to it
 CSeriesRequestGenerator
 CSet
 CSETranslatingPortProxy
 CShader
 CSimObjectAbstract superclass for simulation objects
 CSimObjectResolverBase class to wrap object resolving functionality
 CSimpleCacheA very simple cache object
 CSimpleCPUPolicyStruct that defines the key classes to be used by the CPU
 CSimpleDisk
 CSimpleExecContext
 CSimpleExtLink
 CSimpleFreeListFree list for a single class of registers (e.g., integer or floating point)
 CSimpleIntLink
 CSimpleMemobjA very simple memory object
 CSimpleMemoryThe simple memory is a basic single-ported memory controller with a configurable throughput and latency
 CSimpleNetwork
 CSimpleObject
 CSimplePoolManager
 CSimpleRenameMapRegister rename map for a single class of registers (e.g., integer or floating point)
 CSimpleThreadThe SimpleThread object provides a combination of the ThreadState object and the ThreadContext interface
 CSimpleTimingPortThe simple timing port uses a queued port to implement recvFunctional and recvTimingReq through recvAtomic
 CSimpleTrace
 CSimPoint
 CSkipFuncEvent
 CSlavePortA SlavePort is a specialisation of a port
 CSNHash
 CSnoopFilterThis snoop filter keeps track of which connected port has a particular line of data
 CSnoopRespPacketQueue
 CSolarisThis class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Solaris syscall interface
 CSouthBridge
 CSp804
 CSparc32Linux
 CSparc32Process
 CSparc64Process
 CSparcLinux
 CSparcProcess
 CSparcSolaris
 CSparcSystem
 CSrcClockDomainThe source clock domains provides the notion of a clock domain that is connected to a tunable clock source
 CSRegOperand
 CStackDistCalcThe stack distance calculator is a passive object that merely observes the addresses pass to it
 CStackDistProbe
 CStaticInstBase, ISA-independent static instruction class
 CStatTest
 CStorageElement
 CStorageMap
 CStorageSpace
 CStoreSetImplements a store set predictor for determining if memory instructions are dependent upon each other
 CStoreTrace
 CStridePrefetcher
 CStringWrap
 CStubSlavePortImplement a `stub' port which just responds to requests by printing a message
 CStubSlavePortHandler
 CSubBlock
 CSubSystemThe SubSystem simobject does nothing, it is just a container for other simobjects used by the configuration system
 CSwitch
 CSwitchAllocator
 CSymbolTable
 CSyscallDescThis class provides the wrapper interface for the system call implementations which are defined in the sim/syscall_emul files and bound to the ISAs in the architecture specific code (i.e
 CSyscallFlagTransTableThis struct is used to build target-OS-dependent tables that map the target's flags to the host's flags
 CSyscallRetryFault
 CSyscallReturnThis class represents the return value from an emulated system call, including any errno setting
 CSystem
 CSystemCounterGlobal system counter
 CT1000
 CTaggedPrefetcher
 CTapEvent
 CTapListener
 CTBETable
 CTCPIface
 CTerminal
 CTestClass
 CThermalCapacitorA ThermalCapacitor is used to model a thermal capacitance between two thermal domains
 CThermalDomainA ThermalDomain is used to group objects under that operate under the same temperature
 CThermalEntityAn abstract class that represents any thermal entity which is used in the circuital thermal equivalent model
 CThermalModel
 CThermalNodeA ThermalNode is used to connect thermal entities, such as resistors, capacitors, references and domains
 CThermalReferenceA ThermalReference is a thermal domain with fixed temperature
 CThermalResistorA ThermalResistor is used to model a thermal resistance between two thermal domains
 CThreadContextThreadContext is the external interface to all thread state for anything outside of the CPU
 CThreadStateStruct for holding general thread state that is needed across CPU models
 CThrottle
 CTickedTicked attaches gem5's event queue/scheduler to evaluate calls and provides a start/stop interface to ticking
 CTickedObjectTickedObject attaches Ticked to ClockedObject and can be used as a base class where ticked operation
 CTime
 CTimeBuffer
 CTimeBufStructStruct that defines all backwards communication
 CTimerTable
 CTimingExpr
 CTimingExprBin
 CTimingExprEvalContextObject to gather the visible context for evaluation
 CTimingExprIf
 CTimingExprLet
 CTimingExprLiteral
 CTimingExprReadIntReg
 CTimingExprRef
 CTimingExprSrcReg
 CTimingExprUn
 CTimingSimpleCPU
 CTIR
 CTLBCoalescerThe TLBCoalescer is a MemObject sitting on the front side (CPUSide) of each TLB
 CTopology
 CTournamentBPImplements a tournament branch predictor, hopefully identical to the one used in the 21264
 CTraceCPUThe trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model
 CTraceGenThe trace replay generator reads a trace file and plays back the transactions
 CTraceRecordClass for recording cache contents
 CTrafficGenThe traffic generator is a master module that generates stimuli for the memory system, based on a collection of simple generator behaviours that are either probabilistic or based on traces
 CTrie
 CTrieTestData
 CTsunamiTop level class for Tsunami Chipset emulation
 CTsunamiCChipTsunami CChip CSR Emulation
 CTsunamiIOTsunami I/O device is a catch all for all the south bridge stuff we care to implement
 CTsunamiPChipA very simple implementation of the Tsunami PCI interface chips
 CTypedAtomicOpFunctor
 CTypedBufferArgTypedBufferArg is a class template; instances of this template represent typed buffers in target user space that are passed by reference to an (emulated) system call
 CUart
 CUart8250
 CUFSHostDeviceUFS command flow state machine digraph CommandFlow{ node [fontsize=10]; IDLE -> transferHandler [ label=" transfer/task/command request " fontsize=6]; transferHandler -> command [ label=" It is a command " fontsize=6]; command -> IDLE [ label=" Command done, no further action " fontsize=6]; transferHandler -> taskStart [ label=" It is a task " fontsize=6]; taskStart -> finalUTP [ label=" Task handled, now acknowledge (UFS) " fontsize=6]; transferHandler -> transferStart [ label=" It is a transfer " fontsize=6]; transferStart -> SCSIResume [ label=" Transfer, obtain the specific command " fontsize=6]; SCSIResume -> DiskDataFlowPhase [ label=" Disk data transfer (see other graphs) " fontsize=6]; SCSIResume -> DeviceDataPhase [ label=" Device info transfer (handled in SCSIResume) " fontsize=6]; DiskDataFlowPhase -> transferDone [ label=" Transfer done, acknowledge SCSI command " fontsize=6]; DeviceDataPhase -> transferDone [ label=" Transfer done, acknowledge SCSI command " fontsize=6]; transferDone -> finalUTP [ label=" Transfer handled, now acknowledge (UFS) " fontsize=6]; finalUTP -> readDone [ label=" All handled, clear data structures " fontsize=6]; readDone -> IDLE [ label=" All handled, nothing outstanding " fontsize=6]; readDone -> transferHandler [ label=" All handled, handle next outstanding " fontsize=6]; }
 CUnifiedFreeListFreeList class that simply holds the list of free integer and floating point registers
 CUnifiedRenameMapUnified register rename map for all classes of registers
 CUnimpFault
 CUnknownOp
 CUnknownOp64
 CUserDesc64
 CVecLaneTVector Lane abstraction Another view of a container
 CVecRegContainerVector Register Abstraction This generic class is the model in a particularization of MVC, to vector registers
 CVecRegisterState
 CVecRegTVector Register Abstraction This generic class is a view in a particularization of MVC, to vector registers
 CVectorRegisterFile
 CVGic
 CVIPERCoalescer
 CVirtDescriptorVirtIO descriptor (chain) wrapper
 CVirtIO9PBaseThis class implements a VirtIO transport layer for the 9p network file system
 CVirtIO9PDiodVirtIO 9p proxy that communicates with the diod 9p server using pipes
 CVirtIO9PProxyVirtIO 9p proxy base class
 CVirtIO9PSocketVirtIO 9p proxy that communicates with a 9p server over tcp sockets
 CVirtIOBlockVirtIO block device
 CVirtIOConsoleVirtIO console
 CVirtIODeviceBaseBase class for all VirtIO-based devices
 CVirtIODummyDevice
 CVirtQueueBase wrapper around a virtqueue
 CVirtualChannel
 CVncInput
 CVncKeyboardA device that expects to receive input from the vnc server should derrive (through mulitple inheritence if necessary from VncKeyboard or VncMouse and call setKeyboard() or setMouse() respectively on the vnc server
 CVncMouse
 CVncServer
 CVoltageDomainA VoltageDomain is used to group clock domains that operate under the same voltage
 CVPtr
 Cvring
 Cvring_avail
 Cvring_desc
 Cvring_used
 Cvring_used_elem
 CWaitClass
 CWarnUnimplementedBase class for unimplemented instructions that cause a warning to be printed (but do not terminate simulation)
 CWavefront
 CWeightedLRUPolicy
 CWholeTranslationStateThis class captures the state of an address translation
 CWireBuffer
 CWriteMask
 CWriteQueueA write queue for all eviction packets, i.e
 CWriteQueueEntryWrite queue entry
 CX86KvmCPUX86 implementation of a KVM-based hardware virtualized CPU
 CX86Linux32
 CX86Linux64
 CX86System

Generated on Fri Apr 20 2018 09:05:16 for gem5 by doxygen 1.8.13