gem5
miscregs.hh
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1 /*
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14  * Copyright (c) 2009 The Regents of The University of Michigan
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34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  *
40  * Authors: Gabe Black
41  * Giacomo Gabrielli
42  */
43 #ifndef __ARCH_ARM_MISCREGS_HH__
44 #define __ARCH_ARM_MISCREGS_HH__
45 
46 #include <bitset>
47 #include <tuple>
48 
49 #include "base/bitunion.hh"
50 #include "base/compiler.hh"
51 
52 class ThreadContext;
53 
54 
55 namespace ArmISA
56 {
57  enum MiscRegIndex {
58  MISCREG_CPSR = 0, // 0
73 
74  // Helper registers
90 
91  // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
137  MISCREG_TEECR, // 75, not in ARM DDI 0487A.b+
139  MISCREG_TEEHBR, // 77, not in ARM DDI 0487A.b+
142 
143  // AArch32 CP15 registers (system control)
145  MISCREG_CTR, // 81
166  MISCREG_AIDR, // 102
179  MISCREG_SCR, // 115
180  MISCREG_SDER, // 116
184  MISCREG_HCR, // 120
185  MISCREG_HDCR, // 121
187  MISCREG_HSTR, // 123
188  MISCREG_HACR, // 124
198  MISCREG_HTCR, // 134
199  MISCREG_VTCR, // 135
200  MISCREG_DACR, // 136
203  MISCREG_DFSR, // 139
206  MISCREG_IFSR, // 142
217  MISCREG_HSR, // 153
218  MISCREG_DFAR, // 154
221  MISCREG_IFAR, // 157
229  MISCREG_PAR, // 165
286  MISCREG_PMCR, // 222
304  MISCREG_PRRR, // 240
310  MISCREG_NMRR, // 246
326  MISCREG_VBAR, // 262
330  MISCREG_RMR, // 266
331  MISCREG_ISR, // 267
371  MISCREG_CBAR, // 307
384 
385  // AArch64 registers (Op0=2)
424  MISCREG_TEECR32_EL1, // 358, not in ARM DDI 0487A.b+
425  MISCREG_TEEHBR32_EL1, // 359, not in ARM DDI 0487A.b+
426 
427  // AArch64 registers (Op0=1,3)
497  MISCREG_NZCV, // 429
498  MISCREG_DAIF, // 430
499  MISCREG_FPCR, // 431
500  MISCREG_FPSR, // 432
668 
669  // Introduced in ARMv8.1
671 
672  // These MISCREG_FREESLOT are available Misc Register
673  // slots for future registers to be implemented.
679 
680  // NUM_PHYS_MISCREGS specifies the number of actual physical
681  // registers, not considering the following pseudo-registers
682  // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL.
683  // Checkpointing should use this physical index when
684  // saving/restoring register values.
685  NUM_PHYS_MISCREGS = 606, // 606
686 
687  // Dummy registers
694 
695  // Implementation defined register: this represent
696  // a pool of unimplemented registers whose access can throw
697  // either UNDEFINED or hypervisor trap exception.
699 
700  // Total number of Misc Registers: Physical + Dummy
702  };
703 
704  enum MiscRegInfo {
706  MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
707  // arch generic counter)
708  MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it
709  // tells whether the instruction should raise a
710  // warning or fail
711  MISCREG_MUTEX, // True if the register corresponds to a pair of
712  // mutually exclusive registers
713  MISCREG_BANKED, // True if the register is banked between the two
714  // security states, and this is the parent node of the
715  // two banked registers
716  MISCREG_BANKED_CHILD, // The entry is one of the child registers that
717  // forms a banked set of regs (along with the
718  // other child regs)
719 
720  // Access permissions
721  // User mode
726  // Privileged modes other than hypervisor or monitor
731  // Hypervisor mode
734  // Monitor mode, SCR.NS == 0
737  // Monitor mode, SCR.NS == 1
740 
742  };
743 
744  extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
745 
746  // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
747  MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
748  unsigned crm, unsigned opc2);
749  MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
750  unsigned crn, unsigned crm,
751  unsigned op2);
752  // Whether a particular AArch64 system register is -always- read only.
753  bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
754 
755  // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
756  MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
757  unsigned crm, unsigned opc2);
758 
759  // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
760  MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
761 
762 
763  const char * const miscRegName[] = {
764  "cpsr",
765  "spsr",
766  "spsr_fiq",
767  "spsr_irq",
768  "spsr_svc",
769  "spsr_mon",
770  "spsr_abt",
771  "spsr_hyp",
772  "spsr_und",
773  "elr_hyp",
774  "fpsid",
775  "fpscr",
776  "mvfr1",
777  "mvfr0",
778  "fpexc",
779 
780  // Helper registers
781  "cpsr_mode",
782  "cpsr_q",
783  "fpscr_exc",
784  "fpscr_qc",
785  "lockaddr",
786  "lockflag",
787  "prrr_mair0",
788  "prrr_mair0_ns",
789  "prrr_mair0_s",
790  "nmrr_mair1",
791  "nmrr_mair1_ns",
792  "nmrr_mair1_s",
793  "pmxevtyper_pmccfiltr",
794  "sctlr_rst",
795  "sev_mailbox",
796 
797  // AArch32 CP14 registers
798  "dbgdidr",
799  "dbgdscrint",
800  "dbgdccint",
801  "dbgdtrtxint",
802  "dbgdtrrxint",
803  "dbgwfar",
804  "dbgvcr",
805  "dbgdtrrxext",
806  "dbgdscrext",
807  "dbgdtrtxext",
808  "dbgoseccr",
809  "dbgbvr0",
810  "dbgbvr1",
811  "dbgbvr2",
812  "dbgbvr3",
813  "dbgbvr4",
814  "dbgbvr5",
815  "dbgbcr0",
816  "dbgbcr1",
817  "dbgbcr2",
818  "dbgbcr3",
819  "dbgbcr4",
820  "dbgbcr5",
821  "dbgwvr0",
822  "dbgwvr1",
823  "dbgwvr2",
824  "dbgwvr3",
825  "dbgwcr0",
826  "dbgwcr1",
827  "dbgwcr2",
828  "dbgwcr3",
829  "dbgdrar",
830  "dbgbxvr4",
831  "dbgbxvr5",
832  "dbgoslar",
833  "dbgoslsr",
834  "dbgosdlr",
835  "dbgprcr",
836  "dbgdsar",
837  "dbgclaimset",
838  "dbgclaimclr",
839  "dbgauthstatus",
840  "dbgdevid2",
841  "dbgdevid1",
842  "dbgdevid0",
843  "teecr",
844  "jidr",
845  "teehbr",
846  "joscr",
847  "jmcr",
848 
849  // AArch32 CP15 registers
850  "midr",
851  "ctr",
852  "tcmtr",
853  "tlbtr",
854  "mpidr",
855  "revidr",
856  "id_pfr0",
857  "id_pfr1",
858  "id_dfr0",
859  "id_afr0",
860  "id_mmfr0",
861  "id_mmfr1",
862  "id_mmfr2",
863  "id_mmfr3",
864  "id_isar0",
865  "id_isar1",
866  "id_isar2",
867  "id_isar3",
868  "id_isar4",
869  "id_isar5",
870  "ccsidr",
871  "clidr",
872  "aidr",
873  "csselr",
874  "csselr_ns",
875  "csselr_s",
876  "vpidr",
877  "vmpidr",
878  "sctlr",
879  "sctlr_ns",
880  "sctlr_s",
881  "actlr",
882  "actlr_ns",
883  "actlr_s",
884  "cpacr",
885  "scr",
886  "sder",
887  "nsacr",
888  "hsctlr",
889  "hactlr",
890  "hcr",
891  "hdcr",
892  "hcptr",
893  "hstr",
894  "hacr",
895  "ttbr0",
896  "ttbr0_ns",
897  "ttbr0_s",
898  "ttbr1",
899  "ttbr1_ns",
900  "ttbr1_s",
901  "ttbcr",
902  "ttbcr_ns",
903  "ttbcr_s",
904  "htcr",
905  "vtcr",
906  "dacr",
907  "dacr_ns",
908  "dacr_s",
909  "dfsr",
910  "dfsr_ns",
911  "dfsr_s",
912  "ifsr",
913  "ifsr_ns",
914  "ifsr_s",
915  "adfsr",
916  "adfsr_ns",
917  "adfsr_s",
918  "aifsr",
919  "aifsr_ns",
920  "aifsr_s",
921  "hadfsr",
922  "haifsr",
923  "hsr",
924  "dfar",
925  "dfar_ns",
926  "dfar_s",
927  "ifar",
928  "ifar_ns",
929  "ifar_s",
930  "hdfar",
931  "hifar",
932  "hpfar",
933  "icialluis",
934  "bpiallis",
935  "par",
936  "par_ns",
937  "par_s",
938  "iciallu",
939  "icimvau",
940  "cp15isb",
941  "bpiall",
942  "bpimva",
943  "dcimvac",
944  "dcisw",
945  "ats1cpr",
946  "ats1cpw",
947  "ats1cur",
948  "ats1cuw",
949  "ats12nsopr",
950  "ats12nsopw",
951  "ats12nsour",
952  "ats12nsouw",
953  "dccmvac",
954  "dccsw",
955  "cp15dsb",
956  "cp15dmb",
957  "dccmvau",
958  "dccimvac",
959  "dccisw",
960  "ats1hr",
961  "ats1hw",
962  "tlbiallis",
963  "tlbimvais",
964  "tlbiasidis",
965  "tlbimvaais",
966  "tlbimvalis",
967  "tlbimvaalis",
968  "itlbiall",
969  "itlbimva",
970  "itlbiasid",
971  "dtlbiall",
972  "dtlbimva",
973  "dtlbiasid",
974  "tlbiall",
975  "tlbimva",
976  "tlbiasid",
977  "tlbimvaa",
978  "tlbimval",
979  "tlbimvaal",
980  "tlbiipas2is",
981  "tlbiipas2lis",
982  "tlbiallhis",
983  "tlbimvahis",
984  "tlbiallnsnhis",
985  "tlbimvalhis",
986  "tlbiipas2",
987  "tlbiipas2l",
988  "tlbiallh",
989  "tlbimvah",
990  "tlbiallnsnh",
991  "tlbimvalh",
992  "pmcr",
993  "pmcntenset",
994  "pmcntenclr",
995  "pmovsr",
996  "pmswinc",
997  "pmselr",
998  "pmceid0",
999  "pmceid1",
1000  "pmccntr",
1001  "pmxevtyper",
1002  "pmccfiltr",
1003  "pmxevcntr",
1004  "pmuserenr",
1005  "pmintenset",
1006  "pmintenclr",
1007  "pmovsset",
1008  "l2ctlr",
1009  "l2ectlr",
1010  "prrr",
1011  "prrr_ns",
1012  "prrr_s",
1013  "mair0",
1014  "mair0_ns",
1015  "mair0_s",
1016  "nmrr",
1017  "nmrr_ns",
1018  "nmrr_s",
1019  "mair1",
1020  "mair1_ns",
1021  "mair1_s",
1022  "amair0",
1023  "amair0_ns",
1024  "amair0_s",
1025  "amair1",
1026  "amair1_ns",
1027  "amair1_s",
1028  "hmair0",
1029  "hmair1",
1030  "hamair0",
1031  "hamair1",
1032  "vbar",
1033  "vbar_ns",
1034  "vbar_s",
1035  "mvbar",
1036  "rmr",
1037  "isr",
1038  "hvbar",
1039  "fcseidr",
1040  "contextidr",
1041  "contextidr_ns",
1042  "contextidr_s",
1043  "tpidrurw",
1044  "tpidrurw_ns",
1045  "tpidrurw_s",
1046  "tpidruro",
1047  "tpidruro_ns",
1048  "tpidruro_s",
1049  "tpidrprw",
1050  "tpidrprw_ns",
1051  "tpidrprw_s",
1052  "htpidr",
1053  "cntfrq",
1054  "cntkctl",
1055  "cntp_tval",
1056  "cntp_tval_ns",
1057  "cntp_tval_s",
1058  "cntp_ctl",
1059  "cntp_ctl_ns",
1060  "cntp_ctl_s",
1061  "cntv_tval",
1062  "cntv_ctl",
1063  "cnthctl",
1064  "cnthp_tval",
1065  "cnthp_ctl",
1066  "il1data0",
1067  "il1data1",
1068  "il1data2",
1069  "il1data3",
1070  "dl1data0",
1071  "dl1data1",
1072  "dl1data2",
1073  "dl1data3",
1074  "dl1data4",
1075  "ramindex",
1076  "l2actlr",
1077  "cbar",
1078  "httbr",
1079  "vttbr",
1080  "cntpct",
1081  "cntvct",
1082  "cntp_cval",
1083  "cntp_cval_ns",
1084  "cntp_cval_s",
1085  "cntv_cval",
1086  "cntvoff",
1087  "cnthp_cval",
1088  "cpumerrsr",
1089  "l2merrsr",
1090 
1091  // AArch64 registers (Op0=2)
1092  "mdccint_el1",
1093  "osdtrrx_el1",
1094  "mdscr_el1",
1095  "osdtrtx_el1",
1096  "oseccr_el1",
1097  "dbgbvr0_el1",
1098  "dbgbvr1_el1",
1099  "dbgbvr2_el1",
1100  "dbgbvr3_el1",
1101  "dbgbvr4_el1",
1102  "dbgbvr5_el1",
1103  "dbgbcr0_el1",
1104  "dbgbcr1_el1",
1105  "dbgbcr2_el1",
1106  "dbgbcr3_el1",
1107  "dbgbcr4_el1",
1108  "dbgbcr5_el1",
1109  "dbgwvr0_el1",
1110  "dbgwvr1_el1",
1111  "dbgwvr2_el1",
1112  "dbgwvr3_el1",
1113  "dbgwcr0_el1",
1114  "dbgwcr1_el1",
1115  "dbgwcr2_el1",
1116  "dbgwcr3_el1",
1117  "mdccsr_el0",
1118  "mddtr_el0",
1119  "mddtrtx_el0",
1120  "mddtrrx_el0",
1121  "dbgvcr32_el2",
1122  "mdrar_el1",
1123  "oslar_el1",
1124  "oslsr_el1",
1125  "osdlr_el1",
1126  "dbgprcr_el1",
1127  "dbgclaimset_el1",
1128  "dbgclaimclr_el1",
1129  "dbgauthstatus_el1",
1130  "teecr32_el1",
1131  "teehbr32_el1",
1132 
1133  // AArch64 registers (Op0=1,3)
1134  "midr_el1",
1135  "mpidr_el1",
1136  "revidr_el1",
1137  "id_pfr0_el1",
1138  "id_pfr1_el1",
1139  "id_dfr0_el1",
1140  "id_afr0_el1",
1141  "id_mmfr0_el1",
1142  "id_mmfr1_el1",
1143  "id_mmfr2_el1",
1144  "id_mmfr3_el1",
1145  "id_isar0_el1",
1146  "id_isar1_el1",
1147  "id_isar2_el1",
1148  "id_isar3_el1",
1149  "id_isar4_el1",
1150  "id_isar5_el1",
1151  "mvfr0_el1",
1152  "mvfr1_el1",
1153  "mvfr2_el1",
1154  "id_aa64pfr0_el1",
1155  "id_aa64pfr1_el1",
1156  "id_aa64dfr0_el1",
1157  "id_aa64dfr1_el1",
1158  "id_aa64afr0_el1",
1159  "id_aa64afr1_el1",
1160  "id_aa64isar0_el1",
1161  "id_aa64isar1_el1",
1162  "id_aa64mmfr0_el1",
1163  "id_aa64mmfr1_el1",
1164  "ccsidr_el1",
1165  "clidr_el1",
1166  "aidr_el1",
1167  "csselr_el1",
1168  "ctr_el0",
1169  "dczid_el0",
1170  "vpidr_el2",
1171  "vmpidr_el2",
1172  "sctlr_el1",
1173  "actlr_el1",
1174  "cpacr_el1",
1175  "sctlr_el2",
1176  "actlr_el2",
1177  "hcr_el2",
1178  "mdcr_el2",
1179  "cptr_el2",
1180  "hstr_el2",
1181  "hacr_el2",
1182  "sctlr_el3",
1183  "actlr_el3",
1184  "scr_el3",
1185  "sder32_el3",
1186  "cptr_el3",
1187  "mdcr_el3",
1188  "ttbr0_el1",
1189  "ttbr1_el1",
1190  "tcr_el1",
1191  "ttbr0_el2",
1192  "tcr_el2",
1193  "vttbr_el2",
1194  "vtcr_el2",
1195  "ttbr0_el3",
1196  "tcr_el3",
1197  "dacr32_el2",
1198  "spsr_el1",
1199  "elr_el1",
1200  "sp_el0",
1201  "spsel",
1202  "currentel",
1203  "nzcv",
1204  "daif",
1205  "fpcr",
1206  "fpsr",
1207  "dspsr_el0",
1208  "dlr_el0",
1209  "spsr_el2",
1210  "elr_el2",
1211  "sp_el1",
1212  "spsr_irq_aa64",
1213  "spsr_abt_aa64",
1214  "spsr_und_aa64",
1215  "spsr_fiq_aa64",
1216  "spsr_el3",
1217  "elr_el3",
1218  "sp_el2",
1219  "afsr0_el1",
1220  "afsr1_el1",
1221  "esr_el1",
1222  "ifsr32_el2",
1223  "afsr0_el2",
1224  "afsr1_el2",
1225  "esr_el2",
1226  "fpexc32_el2",
1227  "afsr0_el3",
1228  "afsr1_el3",
1229  "esr_el3",
1230  "far_el1",
1231  "far_el2",
1232  "hpfar_el2",
1233  "far_el3",
1234  "ic_ialluis",
1235  "par_el1",
1236  "ic_iallu",
1237  "dc_ivac_xt",
1238  "dc_isw_xt",
1239  "at_s1e1r_xt",
1240  "at_s1e1w_xt",
1241  "at_s1e0r_xt",
1242  "at_s1e0w_xt",
1243  "dc_csw_xt",
1244  "dc_cisw_xt",
1245  "dc_zva_xt",
1246  "ic_ivau_xt",
1247  "dc_cvac_xt",
1248  "dc_cvau_xt",
1249  "dc_civac_xt",
1250  "at_s1e2r_xt",
1251  "at_s1e2w_xt",
1252  "at_s12e1r_xt",
1253  "at_s12e1w_xt",
1254  "at_s12e0r_xt",
1255  "at_s12e0w_xt",
1256  "at_s1e3r_xt",
1257  "at_s1e3w_xt",
1258  "tlbi_vmalle1is",
1259  "tlbi_vae1is_xt",
1260  "tlbi_aside1is_xt",
1261  "tlbi_vaae1is_xt",
1262  "tlbi_vale1is_xt",
1263  "tlbi_vaale1is_xt",
1264  "tlbi_vmalle1",
1265  "tlbi_vae1_xt",
1266  "tlbi_aside1_xt",
1267  "tlbi_vaae1_xt",
1268  "tlbi_vale1_xt",
1269  "tlbi_vaale1_xt",
1270  "tlbi_ipas2e1is_xt",
1271  "tlbi_ipas2le1is_xt",
1272  "tlbi_alle2is",
1273  "tlbi_vae2is_xt",
1274  "tlbi_alle1is",
1275  "tlbi_vale2is_xt",
1276  "tlbi_vmalls12e1is",
1277  "tlbi_ipas2e1_xt",
1278  "tlbi_ipas2le1_xt",
1279  "tlbi_alle2",
1280  "tlbi_vae2_xt",
1281  "tlbi_alle1",
1282  "tlbi_vale2_xt",
1283  "tlbi_vmalls12e1",
1284  "tlbi_alle3is",
1285  "tlbi_vae3is_xt",
1286  "tlbi_vale3is_xt",
1287  "tlbi_alle3",
1288  "tlbi_vae3_xt",
1289  "tlbi_vale3_xt",
1290  "pmintenset_el1",
1291  "pmintenclr_el1",
1292  "pmcr_el0",
1293  "pmcntenset_el0",
1294  "pmcntenclr_el0",
1295  "pmovsclr_el0",
1296  "pmswinc_el0",
1297  "pmselr_el0",
1298  "pmceid0_el0",
1299  "pmceid1_el0",
1300  "pmccntr_el0",
1301  "pmxevtyper_el0",
1302  "pmccfiltr_el0",
1303  "pmxevcntr_el0",
1304  "pmuserenr_el0",
1305  "pmovsset_el0",
1306  "mair_el1",
1307  "amair_el1",
1308  "mair_el2",
1309  "amair_el2",
1310  "mair_el3",
1311  "amair_el3",
1312  "l2ctlr_el1",
1313  "l2ectlr_el1",
1314  "vbar_el1",
1315  "rvbar_el1",
1316  "isr_el1",
1317  "vbar_el2",
1318  "rvbar_el2",
1319  "vbar_el3",
1320  "rvbar_el3",
1321  "rmr_el3",
1322  "contextidr_el1",
1323  "tpidr_el1",
1324  "tpidr_el0",
1325  "tpidrro_el0",
1326  "tpidr_el2",
1327  "tpidr_el3",
1328  "cntkctl_el1",
1329  "cntfrq_el0",
1330  "cntpct_el0",
1331  "cntvct_el0",
1332  "cntp_tval_el0",
1333  "cntp_ctl_el0",
1334  "cntp_cval_el0",
1335  "cntv_tval_el0",
1336  "cntv_ctl_el0",
1337  "cntv_cval_el0",
1338  "pmevcntr0_el0",
1339  "pmevcntr1_el0",
1340  "pmevcntr2_el0",
1341  "pmevcntr3_el0",
1342  "pmevcntr4_el0",
1343  "pmevcntr5_el0",
1344  "pmevtyper0_el0",
1345  "pmevtyper1_el0",
1346  "pmevtyper2_el0",
1347  "pmevtyper3_el0",
1348  "pmevtyper4_el0",
1349  "pmevtyper5_el0",
1350  "cntvoff_el2",
1351  "cnthctl_el2",
1352  "cnthp_tval_el2",
1353  "cnthp_ctl_el2",
1354  "cnthp_cval_el2",
1355  "cntps_tval_el1",
1356  "cntps_ctl_el1",
1357  "cntps_cval_el1",
1358  "il1data0_el1",
1359  "il1data1_el1",
1360  "il1data2_el1",
1361  "il1data3_el1",
1362  "dl1data0_el1",
1363  "dl1data1_el1",
1364  "dl1data2_el1",
1365  "dl1data3_el1",
1366  "dl1data4_el1",
1367  "l2actlr_el1",
1368  "cpuactlr_el1",
1369  "cpuectlr_el1",
1370  "cpumerrsr_el1",
1371  "l2merrsr_el1",
1372  "cbar_el1",
1373  "contextidr_el2",
1374 
1375  "ttbr1_el2",
1376  "freeslot1",
1377  "freeslot2",
1378  "freeslot3",
1379  "freeslot4",
1380  "freeslot5",
1381 
1382  "num_phys_regs",
1383 
1384  // Dummy registers
1385  "nop",
1386  "raz",
1387  "cp14_unimpl",
1388  "cp15_unimpl",
1389  "a64_unimpl",
1390  "unknown",
1391  "impl_defined"
1392  };
1393 
1394  static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1395  "The miscRegName array and NUM_MISCREGS are inconsistent.");
1396 
1397  BitUnion32(CPSR)
1398  Bitfield<31, 30> nz;
1399  Bitfield<29> c;
1400  Bitfield<28> v;
1401  Bitfield<27> q;
1402  Bitfield<26, 25> it1;
1403  Bitfield<24> j;
1404  Bitfield<23, 22> res0_23_22;
1405  Bitfield<21> ss; // AArch64
1406  Bitfield<20> il; // AArch64
1407  Bitfield<19, 16> ge;
1408  Bitfield<15, 10> it2;
1409  Bitfield<9> d; // AArch64
1410  Bitfield<9> e;
1411  Bitfield<8> a;
1412  Bitfield<7> i;
1413  Bitfield<6> f;
1414  Bitfield<8, 6> aif;
1415  Bitfield<9, 6> daif; // AArch64
1416  Bitfield<5> t;
1417  Bitfield<4> width; // AArch64
1418  Bitfield<3, 2> el; // AArch64
1419  Bitfield<4, 0> mode;
1420  Bitfield<0> sp; // AArch64
1421  EndBitUnion(CPSR)
1422 
1423  // This mask selects bits of the CPSR that actually go in the CondCodes
1424  // integer register to allow renaming.
1425  static const uint32_t CondCodesMask = 0xF00F0000;
1426  static const uint32_t CpsrMaskQ = 0x08000000;
1427 
1428  BitUnion32(HDCR)
1429  Bitfield<11> tdra;
1430  Bitfield<10> tdosa;
1431  Bitfield<9> tda;
1432  Bitfield<8> tde;
1433  Bitfield<7> hpme;
1434  Bitfield<6> tpm;
1435  Bitfield<5> tpmcr;
1436  Bitfield<4, 0> hpmn;
1437  EndBitUnion(HDCR)
1438 
1439  BitUnion32(HCPTR)
1440  Bitfield<31> tcpac;
1441  Bitfield<20> tta;
1442  Bitfield<15> tase;
1443  Bitfield<13> tcp13;
1444  Bitfield<12> tcp12;
1445  Bitfield<11> tcp11;
1446  Bitfield<10> tcp10;
1447  Bitfield<10> tfp; // AArch64
1448  Bitfield<9> tcp9;
1449  Bitfield<8> tcp8;
1450  Bitfield<7> tcp7;
1451  Bitfield<6> tcp6;
1452  Bitfield<5> tcp5;
1453  Bitfield<4> tcp4;
1454  Bitfield<3> tcp3;
1455  Bitfield<2> tcp2;
1456  Bitfield<1> tcp1;
1457  Bitfield<0> tcp0;
1458  EndBitUnion(HCPTR)
1459 
1460  BitUnion32(HSTR)
1461  Bitfield<17> tjdbx;
1462  Bitfield<16> ttee;
1463  Bitfield<15> t15;
1464  Bitfield<13> t13;
1465  Bitfield<12> t12;
1466  Bitfield<11> t11;
1467  Bitfield<10> t10;
1468  Bitfield<9> t9;
1469  Bitfield<8> t8;
1470  Bitfield<7> t7;
1471  Bitfield<6> t6;
1472  Bitfield<5> t5;
1473  Bitfield<4> t4;
1474  Bitfield<3> t3;
1475  Bitfield<2> t2;
1476  Bitfield<1> t1;
1477  Bitfield<0> t0;
1478  EndBitUnion(HSTR)
1479 
1480  BitUnion64(HCR)
1481  Bitfield<33> id; // AArch64
1482  Bitfield<32> cd; // AArch64
1483  Bitfield<31> rw; // AArch64
1484  Bitfield<30> trvm; // AArch64
1485  Bitfield<29> hcd; // AArch64
1486  Bitfield<28> tdz; // AArch64
1487 
1488  Bitfield<27> tge;
1489  Bitfield<26> tvm;
1490  Bitfield<25> ttlb;
1491  Bitfield<24> tpu;
1492  Bitfield<23> tpc;
1493  Bitfield<22> tsw;
1494  Bitfield<21> tac;
1495  Bitfield<21> tacr; // AArch64
1496  Bitfield<20> tidcp;
1497  Bitfield<19> tsc;
1498  Bitfield<18> tid3;
1499  Bitfield<17> tid2;
1500  Bitfield<16> tid1;
1501  Bitfield<15> tid0;
1502  Bitfield<14> twe;
1503  Bitfield<13> twi;
1504  Bitfield<12> dc;
1505  Bitfield<11, 10> bsu;
1506  Bitfield<9> fb;
1507  Bitfield<8> va;
1508  Bitfield<8> vse; // AArch64
1509  Bitfield<7> vi;
1510  Bitfield<6> vf;
1511  Bitfield<5> amo;
1512  Bitfield<4> imo;
1513  Bitfield<3> fmo;
1514  Bitfield<2> ptw;
1515  Bitfield<1> swio;
1516  Bitfield<0> vm;
1517  EndBitUnion(HCR)
1518 
1519  BitUnion32(NSACR)
1520  Bitfield<20> nstrcdis;
1521  Bitfield<19> rfr;
1522  Bitfield<15> nsasedis;
1523  Bitfield<14> nsd32dis;
1524  Bitfield<13> cp13;
1525  Bitfield<12> cp12;
1526  Bitfield<11> cp11;
1527  Bitfield<10> cp10;
1528  Bitfield<9> cp9;
1529  Bitfield<8> cp8;
1530  Bitfield<7> cp7;
1531  Bitfield<6> cp6;
1532  Bitfield<5> cp5;
1533  Bitfield<4> cp4;
1534  Bitfield<3> cp3;
1535  Bitfield<2> cp2;
1536  Bitfield<1> cp1;
1537  Bitfield<0> cp0;
1538  EndBitUnion(NSACR)
1539 
1540  BitUnion32(SCR)
1541  Bitfield<13> twe;
1542  Bitfield<12> twi;
1543  Bitfield<11> st; // AArch64
1544  Bitfield<10> rw; // AArch64
1545  Bitfield<9> sif;
1546  Bitfield<8> hce;
1547  Bitfield<7> scd;
1548  Bitfield<7> smd; // AArch64
1549  Bitfield<6> nEt;
1550  Bitfield<5> aw;
1551  Bitfield<4> fw;
1552  Bitfield<3> ea;
1553  Bitfield<2> fiq;
1554  Bitfield<1> irq;
1555  Bitfield<0> ns;
1556  EndBitUnion(SCR)
1557 
1558  BitUnion32(SCTLR)
1559  Bitfield<30> te; // Thumb Exception Enable (AArch32 only)
1560  Bitfield<29> afe; // Access flag enable (AArch32 only)
1561  Bitfield<28> tre; // TEX remap enable (AArch32 only)
1562  Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only)
1563  Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC,
1564  // DC CVAC and IC IVAU instructions
1565  // (AArch64 SCTLR_EL1 only)
1566  Bitfield<25> ee; // Exception Endianness
1567  Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only)
1568  Bitfield<24> e0e; // Endianness of explicit data accesses at EL0
1569  // (AArch64 SCTLR_EL1 only)
1570  Bitfield<23> xp; // Extended page table enable (dropped in ARMv7)
1571  Bitfield<22> u; // Alignment (dropped in ARMv7)
1572  Bitfield<21> fi; // Fast interrupts configuration enable
1573  // (ARMv7 only)
1574  Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN
1575  // (AArch32 only)
1576  Bitfield<19> dz; // Divide by Zero fault enable
1577  // (dropped in ARMv7)
1578  Bitfield<19> wxn; // Write permission implies XN
1579  Bitfield<18> ntwe; // Not trap WFE
1580  // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1581  Bitfield<18> rao2; // Read as one
1582  Bitfield<16> ntwi; // Not trap WFI
1583  // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1584  Bitfield<16> rao3; // Read as one
1585  Bitfield<15> uct; // Enable EL0 access to CTR_EL0
1586  // (AArch64 SCTLR_EL1 only)
1587  Bitfield<14> rr; // Round Robin select (ARMv7 only)
1588  Bitfield<14> dze; // Enable EL0 access to DC ZVA
1589  // (AArch64 SCTLR_EL1 only)
1590  Bitfield<13> v; // Vectors bit (AArch32 only)
1591  Bitfield<12> i; // Instruction cache enable
1592  Bitfield<11> z; // Branch prediction enable (ARMv7 only)
1593  Bitfield<10> sw; // SWP/SWPB enable (ARMv7 only)
1594  Bitfield<9, 8> rs; // Deprecated protection bits (dropped in ARMv7)
1595  Bitfield<9> uma; // User mask access (AArch64 SCTLR_EL1 only)
1596  Bitfield<8> sed; // SETEND disable
1597  // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1598  Bitfield<7> b; // Endianness support (dropped in ARMv7)
1599  Bitfield<7> itd; // IT disable
1600  // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1601  Bitfield<6, 3> rao4; // Read as one
1602  Bitfield<6> thee; // ThumbEE enable
1603  // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1604  Bitfield<5> cp15ben; // CP15 barrier enable
1605  // (AArch32 and AArch64 SCTLR_EL1 only)
1606  Bitfield<4> sa0; // Stack Alignment Check Enable for EL0
1607  // (AArch64 SCTLR_EL1 only)
1608  Bitfield<3> sa; // Stack Alignment Check Enable (AArch64 only)
1609  Bitfield<2> c; // Cache enable
1610  Bitfield<1> a; // Alignment check enable
1611  Bitfield<0> m; // MMU enable
1612  EndBitUnion(SCTLR)
1613 
1614  BitUnion32(CPACR)
1615  Bitfield<1, 0> cp0;
1616  Bitfield<3, 2> cp1;
1617  Bitfield<5, 4> cp2;
1618  Bitfield<7, 6> cp3;
1619  Bitfield<9, 8> cp4;
1620  Bitfield<11, 10> cp5;
1621  Bitfield<13, 12> cp6;
1622  Bitfield<15, 14> cp7;
1623  Bitfield<17, 16> cp8;
1624  Bitfield<19, 18> cp9;
1625  Bitfield<21, 20> cp10;
1626  Bitfield<21, 20> fpen; // AArch64
1627  Bitfield<23, 22> cp11;
1628  Bitfield<25, 24> cp12;
1629  Bitfield<27, 26> cp13;
1630  Bitfield<29, 28> rsvd;
1631  Bitfield<28> tta; // AArch64
1632  Bitfield<30> d32dis;
1633  Bitfield<31> asedis;
1634  EndBitUnion(CPACR)
1635 
1636  BitUnion32(FSR)
1637  Bitfield<3, 0> fsLow;
1638  Bitfield<5, 0> status; // LPAE
1639  Bitfield<7, 4> domain;
1640  Bitfield<9> lpae;
1641  Bitfield<10> fsHigh;
1642  Bitfield<11> wnr;
1643  Bitfield<12> ext;
1644  Bitfield<13> cm; // LPAE
1645  EndBitUnion(FSR)
1646 
1647  BitUnion32(FPSCR)
1648  Bitfield<0> ioc;
1649  Bitfield<1> dzc;
1650  Bitfield<2> ofc;
1651  Bitfield<3> ufc;
1652  Bitfield<4> ixc;
1653  Bitfield<7> idc;
1654  Bitfield<8> ioe;
1655  Bitfield<9> dze;
1656  Bitfield<10> ofe;
1657  Bitfield<11> ufe;
1658  Bitfield<12> ixe;
1659  Bitfield<15> ide;
1660  Bitfield<18, 16> len;
1661  Bitfield<21, 20> stride;
1662  Bitfield<23, 22> rMode;
1663  Bitfield<24> fz;
1664  Bitfield<25> dn;
1665  Bitfield<26> ahp;
1666  Bitfield<27> qc;
1667  Bitfield<28> v;
1668  Bitfield<29> c;
1669  Bitfield<30> z;
1670  Bitfield<31> n;
1671  EndBitUnion(FPSCR)
1672 
1673  // This mask selects bits of the FPSCR that actually go in the FpCondCodes
1674  // integer register to allow renaming.
1675  static const uint32_t FpCondCodesMask = 0xF0000000;
1676  // This mask selects the cumulative FP exception flags of the FPSCR.
1677  static const uint32_t FpscrExcMask = 0x0000009F;
1678  // This mask selects the cumulative saturation flag of the FPSCR.
1679  static const uint32_t FpscrQcMask = 0x08000000;
1680 
1681  BitUnion32(FPEXC)
1682  Bitfield<31> ex;
1683  Bitfield<30> en;
1684  Bitfield<29, 0> subArchDefined;
1685  EndBitUnion(FPEXC)
1686 
1687  BitUnion32(MVFR0)
1688  Bitfield<3, 0> advSimdRegisters;
1689  Bitfield<7, 4> singlePrecision;
1690  Bitfield<11, 8> doublePrecision;
1691  Bitfield<15, 12> vfpExceptionTrapping;
1692  Bitfield<19, 16> divide;
1693  Bitfield<23, 20> squareRoot;
1694  Bitfield<27, 24> shortVectors;
1695  Bitfield<31, 28> roundingModes;
1696  EndBitUnion(MVFR0)
1697 
1698  BitUnion32(MVFR1)
1699  Bitfield<3, 0> flushToZero;
1700  Bitfield<7, 4> defaultNaN;
1701  Bitfield<11, 8> advSimdLoadStore;
1702  Bitfield<15, 12> advSimdInteger;
1703  Bitfield<19, 16> advSimdSinglePrecision;
1704  Bitfield<23, 20> advSimdHalfPrecision;
1705  Bitfield<27, 24> vfpHalfPrecision;
1706  Bitfield<31, 28> raz;
1707  EndBitUnion(MVFR1)
1708 
1709  BitUnion64(TTBCR)
1710  // Short-descriptor translation table format
1711  Bitfield<2, 0> n;
1712  Bitfield<4> pd0;
1713  Bitfield<5> pd1;
1714  // Long-descriptor translation table format
1715  Bitfield<5, 0> t0sz;
1716  Bitfield<7> epd0;
1717  Bitfield<9, 8> irgn0;
1718  Bitfield<11, 10> orgn0;
1719  Bitfield<13, 12> sh0;
1720  Bitfield<14> tg0;
1721  Bitfield<21, 16> t1sz;
1722  Bitfield<22> a1;
1723  Bitfield<23> epd1;
1724  Bitfield<25, 24> irgn1;
1725  Bitfield<27, 26> orgn1;
1726  Bitfield<29, 28> sh1;
1727  Bitfield<30> tg1;
1728  Bitfield<34, 32> ips;
1729  Bitfield<36> as;
1730  Bitfield<37> tbi0;
1731  Bitfield<38> tbi1;
1732  // Common
1733  Bitfield<31> eae;
1734  // TCR_EL2/3 (AArch64)
1735  Bitfield<18, 16> ps;
1736  Bitfield<20> tbi;
1737  EndBitUnion(TTBCR)
1738 
1739  // Fields of TCR_EL{1,2,3} (mostly overlapping)
1740  // TCR_EL1 is natively 64 bits, the others are 32 bits
1741  BitUnion64(TCR)
1742  Bitfield<5, 0> t0sz;
1743  Bitfield<7> epd0; // EL1
1744  Bitfield<9, 8> irgn0;
1745  Bitfield<11, 10> orgn0;
1746  Bitfield<13, 12> sh0;
1747  Bitfield<15, 14> tg0;
1748  Bitfield<18, 16> ps;
1749  Bitfield<20> tbi; // EL2/EL3
1750  Bitfield<21, 16> t1sz; // EL1
1751  Bitfield<22> a1; // EL1
1752  Bitfield<23> epd1; // EL1
1753  Bitfield<25, 24> irgn1; // EL1
1754  Bitfield<27, 26> orgn1; // EL1
1755  Bitfield<29, 28> sh1; // EL1
1756  Bitfield<31, 30> tg1; // EL1
1757  Bitfield<34, 32> ips; // EL1
1758  Bitfield<36> as; // EL1
1759  Bitfield<37> tbi0; // EL1
1760  Bitfield<38> tbi1; // EL1
1761  EndBitUnion(TCR)
1762 
1763  BitUnion32(HTCR)
1764  Bitfield<2, 0> t0sz;
1765  Bitfield<9, 8> irgn0;
1766  Bitfield<11, 10> orgn0;
1767  Bitfield<13, 12> sh0;
1768  EndBitUnion(HTCR)
1769 
1770  BitUnion32(VTCR_t)
1771  Bitfield<3, 0> t0sz;
1772  Bitfield<4> s;
1773  Bitfield<5, 0> t0sz64;
1774  Bitfield<7, 6> sl0;
1775  Bitfield<9, 8> irgn0;
1776  Bitfield<11, 10> orgn0;
1777  Bitfield<13, 12> sh0;
1778  Bitfield<15, 14> tg0;
1779  EndBitUnion(VTCR_t)
1780 
1781  BitUnion32(PRRR)
1782  Bitfield<1,0> tr0;
1783  Bitfield<3,2> tr1;
1784  Bitfield<5,4> tr2;
1785  Bitfield<7,6> tr3;
1786  Bitfield<9,8> tr4;
1787  Bitfield<11,10> tr5;
1788  Bitfield<13,12> tr6;
1789  Bitfield<15,14> tr7;
1790  Bitfield<16> ds0;
1791  Bitfield<17> ds1;
1792  Bitfield<18> ns0;
1793  Bitfield<19> ns1;
1794  Bitfield<24> nos0;
1795  Bitfield<25> nos1;
1796  Bitfield<26> nos2;
1797  Bitfield<27> nos3;
1798  Bitfield<28> nos4;
1799  Bitfield<29> nos5;
1800  Bitfield<30> nos6;
1801  Bitfield<31> nos7;
1802  EndBitUnion(PRRR)
1803 
1804  BitUnion32(NMRR)
1805  Bitfield<1,0> ir0;
1806  Bitfield<3,2> ir1;
1807  Bitfield<5,4> ir2;
1808  Bitfield<7,6> ir3;
1809  Bitfield<9,8> ir4;
1810  Bitfield<11,10> ir5;
1811  Bitfield<13,12> ir6;
1812  Bitfield<15,14> ir7;
1813  Bitfield<17,16> or0;
1814  Bitfield<19,18> or1;
1815  Bitfield<21,20> or2;
1816  Bitfield<23,22> or3;
1817  Bitfield<25,24> or4;
1818  Bitfield<27,26> or5;
1819  Bitfield<29,28> or6;
1820  Bitfield<31,30> or7;
1821  EndBitUnion(NMRR)
1822 
1823  BitUnion32(CONTEXTIDR)
1824  Bitfield<7,0> asid;
1825  Bitfield<31,8> procid;
1826  EndBitUnion(CONTEXTIDR)
1827 
1828  BitUnion32(L2CTLR)
1829  Bitfield<2,0> sataRAMLatency;
1830  Bitfield<4,3> reserved_4_3;
1831  Bitfield<5> dataRAMSetup;
1832  Bitfield<8,6> tagRAMLatency;
1833  Bitfield<9> tagRAMSetup;
1834  Bitfield<11,10> dataRAMSlice;
1835  Bitfield<12> tagRAMSlice;
1836  Bitfield<20,13> reserved_20_13;
1837  Bitfield<21> eccandParityEnable;
1838  Bitfield<22> reserved_22;
1839  Bitfield<23> interptCtrlPresent;
1840  Bitfield<25,24> numCPUs;
1841  Bitfield<30,26> reserved_30_26;
1842  Bitfield<31> l2rstDISABLE_monitor;
1843  EndBitUnion(L2CTLR)
1844 
1845  BitUnion32(CTR)
1846  Bitfield<3,0> iCacheLineSize;
1847  Bitfield<13,4> raz_13_4;
1848  Bitfield<15,14> l1IndexPolicy;
1849  Bitfield<19,16> dCacheLineSize;
1850  Bitfield<23,20> erg;
1851  Bitfield<27,24> cwg;
1852  Bitfield<28> raz_28;
1853  Bitfield<31,29> format;
1854  EndBitUnion(CTR)
1855 
1856  BitUnion32(PMSELR)
1857  Bitfield<4, 0> sel;
1858  EndBitUnion(PMSELR)
1859 
1860  BitUnion64(PAR)
1861  // 64-bit format
1862  Bitfield<63, 56> attr;
1863  Bitfield<39, 12> pa;
1864  Bitfield<11> lpae;
1865  Bitfield<9> ns;
1866  Bitfield<8, 7> sh;
1867  Bitfield<0> f;
1868  EndBitUnion(PAR)
1869 
1870  BitUnion32(ESR)
1871  Bitfield<31, 26> ec;
1872  Bitfield<25> il;
1873  Bitfield<15, 0> imm16;
1874  EndBitUnion(ESR)
1875 
1876  BitUnion32(CPTR)
1877  Bitfield<31> tcpac;
1878  Bitfield<20> tta;
1879  Bitfield<13, 12> res1_13_12_el2;
1880  Bitfield<10> tfp;
1881  Bitfield<9, 0> res1_9_0_el2;
1882  EndBitUnion(CPTR)
1883 
1884 
1898  std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr,
1899  CPSR cpsr);
1900 
1914  std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr,
1915  CPSR cpsr);
1916 
1917  // Checks read access permissions to AArch64 system registers
1918  bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1919  ThreadContext *tc);
1920 
1921  // Checks write access permissions to AArch64 system registers
1922  bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1923  ThreadContext *tc);
1924 
1925  // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
1926  // for MCR/MRC instructions
1927  int
1929 
1930  // Flattens a misc reg index using the specified security state. This is
1931  // used for opperations (eg address translations) where the security
1932  // state of the register access may differ from the current state of the
1933  // processor
1934  int
1935  snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns);
1936 
1937  // Takes a misc reg index and returns the root reg if its one of a set of
1938  // banked registers
1939  void
1941 
1942  int
1943  unflattenMiscReg(int reg);
1944 
1945 }
1946 
1947 #endif // __ARCH_ARM_MISCREGS_HH__
Bitfield< 13, 12 > ir6
Definition: miscregs.hh:1811
std::tuple< bool, bool > canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
Definition: miscregs.cc:789
Bitfield< 31 > asedis
Definition: miscregs.hh:1633
Bitfield< 31, 8 > procid
Definition: miscregs.hh:1825
Bitfield< 23 > tpc
Definition: miscregs.hh:1492
Bitfield< 3, 2 > tr1
Definition: miscregs.hh:1783
Bitfield< 24 > fz
Definition: miscregs.hh:1663
Bitfield< 9, 8 > irgn0
Definition: miscregs.hh:1717
Bitfield< 15 > te
Definition: mt_constants.hh:62
MiscRegIndex
Definition: miscregs.hh:57
bitset< NUM_MISCREG_INFOS > miscRegInfo[NUM_MISCREGS]
Definition: miscregs.cc:2381
Bitfield< 5, 3 > reg
Definition: types.hh:89
Bitfield< 26 > tvm
Definition: miscregs.hh:1489
Bitfield< 28 > v
Definition: miscregs.hh:1400
Bitfield< 8 > hce
Definition: miscregs.hh:1546
Bitfield< 11 > tcp11
Definition: miscregs.hh:1445
Bitfield< 20, 13 > reserved_20_13
Definition: miscregs.hh:1836
Bitfield< 7 > i
Definition: miscregs.hh:1412
Bitfield< 7 > hpme
Definition: miscregs.hh:1433
Bitfield< 0 > m
Definition: miscregs.hh:1611
Bitfield< 29 > hcd
Definition: miscregs.hh:1485
Bitfield< 31, 28 > roundingModes
Definition: miscregs.hh:1695
Bitfield< 2 > t2
Definition: miscregs.hh:1475
Bitfield< 10 > fsHigh
Definition: miscregs.hh:1641
Bitfield< 11 > z
Definition: miscregs.hh:1592
Bitfield< 31 > eae
Definition: miscregs.hh:1733
Bitfield< 9 > tagRAMSetup
Definition: miscregs.hh:1833
Bitfield< 30 > trvm
Definition: miscregs.hh:1484
Bitfield< 15, 14 > l1IndexPolicy
Definition: miscregs.hh:1848
Bitfield< 6 > tpm
Definition: miscregs.hh:1434
Bitfield< 21, 20 > stride
Definition: miscregs.hh:1661
Bitfield< 27, 24 > shortVectors
Definition: miscregs.hh:1694
Bitfield< 8 > a
Definition: miscregs.hh:1411
Bitfield< 17 > tid2
Definition: miscregs.hh:1499
Bitfield< 8, 7 > sh
Definition: miscregs.hh:1866
advSimdRegisters
Definition: miscregs.hh:1688
Bitfield< 21 > tacr
Definition: miscregs.hh:1495
Bitfield< 29, 28 > or6
Definition: miscregs.hh:1819
Bitfield< 8, 6 > aif
Definition: miscregs.hh:1414
Bitfield< 31 > nos7
Definition: miscregs.hh:1801
Bitfield< 5, 4 > tr2
Definition: miscregs.hh:1784
Bitfield< 13 > twi
Definition: miscregs.hh:1503
Bitfield< 0 > sp
Definition: miscregs.hh:1420
Bitfield< 31, 28 > raz
Definition: miscregs.hh:1706
Bitfield< 15, 14 > ir7
Definition: miscregs.hh:1812
Bitfield< 15, 12 > advSimdInteger
Definition: miscregs.hh:1702
Bitfield< 27 > tge
Definition: miscregs.hh:1488
Bitfield< 16 > ttee
Definition: miscregs.hh:1462
Bitfield< 7 > itd
Definition: miscregs.hh:1599
Bitfield< 14 > dze
Definition: miscregs.hh:1588
Bitfield< 26 > uci
Definition: miscregs.hh:1563
Bitfield< 15 > t15
Definition: miscregs.hh:1463
Bitfield< 7 > cp7
Definition: miscregs.hh:1530
Bitfield< 4, 0 > hpmn
Definition: miscregs.hh:1436
Bitfield< 12 > ext
Definition: miscregs.hh:1643
Bitfield< 5 > pd1
Definition: miscregs.hh:1713
Bitfield< 12 > cp12
Definition: miscregs.hh:1525
void preUnflattenMiscReg()
Definition: miscregs.cc:890
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:579
Definition: ccregs.hh:42
Bitfield< 13 > t13
Definition: miscregs.hh:1464
const char *const miscRegName[]
Definition: miscregs.hh:763
Bitfield< 20 > tidcp
Definition: miscregs.hh:1496
Bitfield< 23, 22 > res0_23_22
Definition: miscregs.hh:1404
Bitfield< 4, 0 > mode
Definition: miscregs.hh:1419
Bitfield< 30 > en
Definition: miscregs.hh:1683
Bitfield< 0 > t0
Definition: miscregs.hh:1477
Bitfield< 14 > twe
Definition: miscregs.hh:1502
Bitfield< 19, 16 > divide
Definition: miscregs.hh:1692
Bitfield< 9 > lpae
Definition: miscregs.hh:1640
Bitfield< 5 > dataRAMSetup
Definition: miscregs.hh:1831
Bitfield< 13, 12 > sh0
Definition: miscregs.hh:1719
Bitfield< 1 > cp1
Definition: miscregs.hh:1536
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Bitfield< 11, 8 > doublePrecision
Definition: miscregs.hh:1690
Bitfield< 30 > nos6
Definition: miscregs.hh:1800
Bitfield< 29 > afe
Definition: miscregs.hh:1560
Bitfield< 23 > interptCtrlPresent
Definition: miscregs.hh:1839
Bitfield< 4 > fw
Definition: miscregs.hh:1551
Bitfield< 9, 8 > ir4
Definition: miscregs.hh:1809
Bitfield< 14 > rr
Definition: miscregs.hh:1587
Bitfield< 16 > ds0
Definition: miscregs.hh:1790
Bitfield< 8 > tde
Definition: miscregs.hh:1432
MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1)
Definition: miscregs.cc:742
Bitfield< 18 > ntwe
Definition: miscregs.hh:1579
Bitfield< 31 > n
Definition: miscregs.hh:1670
Bitfield< 15 > uct
Definition: miscregs.hh:1585
Bitfield< 14 > nsd32dis
Definition: miscregs.hh:1523
Bitfield< 22 > reserved_22
Definition: miscregs.hh:1838
Bitfield< 8 > ioe
Definition: miscregs.hh:1654
Bitfield< 6 > f
Definition: miscregs.hh:1413
BitUnion32(CPSR) Bitfield< 31
Bitfield< 24 > e0e
Definition: miscregs.hh:1568
Bitfield< 1 > dzc
Definition: miscregs.hh:1649
Bitfield< 4 > cp4
Definition: miscregs.hh:1533
Bitfield< 10 > sw
Definition: miscregs.hh:1593
Bitfield< 19, 18 > or1
Definition: miscregs.hh:1814
Bitfield< 16 > tid1
Definition: miscregs.hh:1500
Bitfield< 28 > raz_28
Definition: miscregs.hh:1852
Bitfield< 5, 0 > status
Definition: miscregs.hh:1638
Bitfield< 11 > ufe
Definition: miscregs.hh:1657
Bitfield< 5 > cp5
Definition: miscregs.hh:1532
Bitfield< 8 > t8
Definition: miscregs.hh:1469
Bitfield< 27 > nmfi
Definition: miscregs.hh:1562
Bitfield< 21 > eccandParityEnable
Definition: miscregs.hh:1837
Bitfield< 7 > b
Definition: miscregs.hh:1598
Bitfield< 10 > tdosa
Definition: miscregs.hh:1430
Bitfield< 2 > tcp2
Definition: miscregs.hh:1455
Bitfield< 19 > rfr
Definition: miscregs.hh:1521
Bitfield< 8 > cp8
Definition: miscregs.hh:1529
Bitfield< 0 > ns
Definition: miscregs.hh:1555
Bitfield< 21 > fi
Definition: miscregs.hh:1572
Bitfield< 26 > ahp
Definition: miscregs.hh:1665
Bitfield< 4 > tcp4
Definition: miscregs.hh:1453
Bitfield< 21 > tac
Definition: miscregs.hh:1494
Bitfield< 21, 16 > t1sz
Definition: miscregs.hh:1721
Bitfield< 30 > tg1
Definition: miscregs.hh:1727
Bitfield< 3, 2 > el
Definition: miscregs.hh:1418
Bitfield< 5 > tpmcr
Definition: miscregs.hh:1435
int unflattenMiscReg(int reg)
Definition: miscregs.cc:906
Bitfield< 14 > tg0
Definition: miscregs.hh:1720
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
Definition: miscregs.cc:994
Bitfield< 2 > fiq
Definition: miscregs.hh:1553
Bitfield< 3 > cp3
Definition: miscregs.hh:1534
iCacheLineSize
Definition: miscregs.hh:1846
Bitfield< 4 > s
Definition: miscregs.hh:1772
Bitfield< 22 > u
Definition: miscregs.hh:1571
sataRAMLatency
Definition: miscregs.hh:1829
Bitfield< 5 > t5
Definition: miscregs.hh:1472
Bitfield< 11, 8 > advSimdLoadStore
Definition: miscregs.hh:1701
Bitfield< 13 > tcp13
Definition: miscregs.hh:1443
Bitfield< 2 > cp2
Definition: miscregs.hh:1535
Bitfield< 16 > rao3
Definition: miscregs.hh:1584
Bitfield< 13, 12 > res1_13_12_el2
Definition: miscregs.hh:1879
Bitfield< 11, 10 > tr5
Definition: miscregs.hh:1787
Bitfield< 5 > cp15ben
Definition: miscregs.hh:1604
Bitfield< 12 > ixe
Definition: miscregs.hh:1658
Bitfield< 27 > q
Definition: miscregs.hh:1401
Bitfield< 9 > tda
Definition: miscregs.hh:1431
Bitfield< 26, 25 > it1
Definition: miscregs.hh:1402
Bitfield< 5 > aw
Definition: miscregs.hh:1550
Bitfield< 9 > tcp9
Definition: miscregs.hh:1448
Bitfield< 2 > ptw
Definition: miscregs.hh:1514
Bitfield< 9 > d
Definition: miscregs.hh:1409
Bitfield< 7 > smd
Definition: miscregs.hh:1548
Bitfield< 0 > cp0
Definition: miscregs.hh:1537
Bitfield< 16 > ntwi
Definition: miscregs.hh:1582
Bitfield< 3 > t3
Definition: miscregs.hh:1474
Bitfield< 25 > dn
Definition: miscregs.hh:1664
Bitfield< 3 > sa
Definition: miscregs.hh:1608
Bitfield< 19 > ns1
Definition: miscregs.hh:1793
Bitfield< 39, 12 > pa
Definition: miscregs.hh:1863
Bitfield< 11, 10 > orgn0
Definition: miscregs.hh:1718
Bitfield< 24 > ve
Definition: miscregs.hh:1567
Bitfield< 3 > fmo
Definition: miscregs.hh:1513
Bitfield< 15 > tase
Definition: miscregs.hh:1442
Bitfield< 19 > wxn
Definition: miscregs.hh:1578
Bitfield< 24 > nos0
Definition: miscregs.hh:1794
Bitfield< 7, 4 > singlePrecision
Definition: miscregs.hh:1689
Bitfield< 13 > cp13
Definition: miscregs.hh:1524
static const uint32_t CpsrMaskQ
Definition: miscregs.hh:1426
Bitfield< 9, 8 > tr4
Definition: miscregs.hh:1786
Bitfield< 10 > ofe
Definition: miscregs.hh:1656
Bitfield< 9 > sif
Definition: miscregs.hh:1545
Bitfield< 28 > nos4
Definition: miscregs.hh:1798
Bitfield< 30 > d32dis
Definition: miscregs.hh:1632
Bitfield< 7 > scd
Definition: miscregs.hh:1547
Bitfield< 10 > t10
Definition: miscregs.hh:1467
Bitfield< 27 > qc
Definition: miscregs.hh:1666
bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
Definition: miscregs.cc:912
Bitfield< 23, 20 > squareRoot
Definition: miscregs.hh:1693
Bitfield< 7 > idc
Definition: miscregs.hh:1653
Bitfield< 7 > epd0
Definition: miscregs.hh:1716
Bitfield< 23 > xp
Definition: miscregs.hh:1570
Bitfield< 6, 3 > rao4
Definition: miscregs.hh:1601
Bitfield< 11 > wnr
Definition: miscregs.hh:1642
Bitfield< 21 > ss
Definition: miscregs.hh:1405
Bitfield< 28 > tdz
Definition: miscregs.hh:1486
bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
Definition: miscregs.cc:950
Bitfield< 29, 28 > rsvd
Definition: miscregs.hh:1630
Bitfield< 27, 26 > or5
Definition: miscregs.hh:1818
Bitfield< 9 > cp9
Definition: miscregs.hh:1528
Bitfield< 15, 0 > imm16
Definition: miscregs.hh:1873
Bitfield< 9 > uma
Definition: miscregs.hh:1595
Bitfield< 13, 4 > raz_13_4
Definition: miscregs.hh:1847
Bitfield< 7, 4 > defaultNaN
Definition: miscregs.hh:1700
Bitfield< 25, 24 > numCPUs
Definition: miscregs.hh:1840
Bitfield< 5, 4 > ir2
Definition: miscregs.hh:1807
Bitfield< 29, 28 > sh1
Definition: miscregs.hh:1726
Bitfield< 8 > va
Definition: miscregs.hh:1507
Bitfield< 2 > ofc
Definition: miscregs.hh:1650
Bitfield< 6 > t6
Definition: miscregs.hh:1471
Bitfield< 20 > tta
Definition: miscregs.hh:1441
Bitfield< 19, 16 > dCacheLineSize
Definition: miscregs.hh:1849
Bitfield< 25 > ee
Definition: miscregs.hh:1566
Bitfield< 22 > tsw
Definition: miscregs.hh:1493
Bitfield< 7, 6 > ir3
Definition: miscregs.hh:1808
Bitfield< 7, 6 > tr3
Definition: miscregs.hh:1785
MiscRegInfo
Definition: miscregs.hh:704
Bitfield< 24 > j
Definition: miscregs.hh:1403
Bitfield< 7 > vi
Definition: miscregs.hh:1509
Bitfield< 4 > imo
Definition: miscregs.hh:1512
Bitfield< 11, 10 > bsu
Definition: miscregs.hh:1505
Bitfield< 4 > ixc
Definition: miscregs.hh:1652
Bitfield< 25, 24 > irgn1
Definition: miscregs.hh:1724
Bitfield< 36 > as
Definition: miscregs.hh:1729
Bitfield< 9 > e
Definition: miscregs.hh:1410
EndBitUnion(CPSR) static const uint32_t CondCodesMask=0xF00F0000
Bitfield< 3, 2 > ir1
Definition: miscregs.hh:1806
Bitfield< 25 > nos1
Definition: miscregs.hh:1795
Bitfield< 30, 26 > reserved_30_26
Definition: miscregs.hh:1841
Bitfield< 19, 16 > ge
Definition: miscregs.hh:1407
Bitfield< 10 > cp10
Definition: miscregs.hh:1527
Bitfield< 1 > irq
Definition: miscregs.hh:1554
Bitfield< 29 > c
Definition: miscregs.hh:1399
Bitfield< 5, 0 > t0sz64
Definition: miscregs.hh:1773
Bitfield< 6 > tcp6
Definition: miscregs.hh:1451
Bitfield< 4, 3 > reserved_4_3
Definition: miscregs.hh:1830
Bitfield< 9, 6 > daif
Definition: miscregs.hh:1415
Bitfield< 1 > t1
Definition: miscregs.hh:1476
Bitfield< 6 > vf
Definition: miscregs.hh:1510
Bitfield< 17 > ds1
Definition: miscregs.hh:1791
Bitfield< 37 > tbi0
Definition: miscregs.hh:1730
Bitfield< 7, 4 > domain
Definition: miscregs.hh:1639
Bitfield< 17, 16 > or0
Definition: miscregs.hh:1813
Bitfield< 31, 29 > format
Definition: miscregs.hh:1853
Bitfield< 11 > st
Definition: miscregs.hh:1543
Bitfield< 5 > amo
Definition: miscregs.hh:1511
Bitfield< 19, 16 > advSimdSinglePrecision
Definition: miscregs.hh:1703
Bitfield< 23, 20 > advSimdHalfPrecision
Definition: miscregs.hh:1704
Bitfield< 26 > nos2
Definition: miscregs.hh:1796
Bitfield< 15, 12 > vfpExceptionTrapping
Definition: miscregs.hh:1691
Bitfield< 9 > fb
Definition: miscregs.hh:1506
Bitfield< 29 > nos5
Definition: miscregs.hh:1799
std::tuple< bool, bool > canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
Check for permission to read coprocessor registers.
Definition: miscregs.cc:825
Bitfield< 7, 6 > sl0
Definition: miscregs.hh:1774
Bitfield< 18 > rao2
Definition: miscregs.hh:1581
Bitfield< 7 > tcp7
Definition: miscregs.hh:1450
int snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
Definition: miscregs.cc:861
Bitfield< 10 > tfp
Definition: miscregs.hh:1447
Bitfield< 25, 24 > or4
Definition: miscregs.hh:1817
Bitfield< 28 > tre
Definition: miscregs.hh:1561
Bitfield< 15, 14 > tr7
Definition: miscregs.hh:1789
Bitfield< 8, 6 > tagRAMLatency
Definition: miscregs.hh:1832
Bitfield< 18, 16 > len
Definition: miscregs.hh:1660
Bitfield< 4 > width
Definition: miscregs.hh:1417
Bitfield< 13, 12 > tr6
Definition: miscregs.hh:1788
Bitfield< 31 > rw
Definition: miscregs.hh:1483
Bitfield< 5, 0 > t0sz
Definition: miscregs.hh:1715
Bitfield< 18 > ns0
Definition: miscregs.hh:1792
Bitfield< 10 > tcp10
Definition: miscregs.hh:1446
Bitfield< 31, 30 > or7
Definition: miscregs.hh:1820
Bitfield< 24 > tpu
Definition: miscregs.hh:1491
Bitfield< 27, 26 > orgn1
Definition: miscregs.hh:1725
Bitfield< 7, 5 > opc2
Definition: types.hh:111
Bitfield< 13 > cm
Definition: miscregs.hh:1644
bool aarch64SysRegReadOnly(MiscRegIndex miscReg)
Bitfield< 1 > swio
Definition: miscregs.hh:1515
Bitfield< 34, 32 > ips
Definition: miscregs.hh:1728
Bitfield< 7 > t7
Definition: miscregs.hh:1470
Bitfield< 4 > t4
Definition: miscregs.hh:1473
Bitfield< 27, 24 > vfpHalfPrecision
Definition: miscregs.hh:1705
static const uint32_t FpscrExcMask
Definition: miscregs.hh:1677
Bitfield< 5 > tcp5
Definition: miscregs.hh:1452
Bitfield< 23, 22 > or3
Definition: miscregs.hh:1816
Bitfield< 6 > cp6
Definition: miscregs.hh:1531
Bitfield< 32 > cd
Definition: miscregs.hh:1482
Bitfield< 12 > t12
Definition: miscregs.hh:1465
Bitfield< 19 > tsc
Definition: miscregs.hh:1497
Bitfield< 25 > ttlb
Definition: miscregs.hh:1490
Bitfield< 11, 10 > dataRAMSlice
Definition: miscregs.hh:1834
Bitfield< 8 > tcp8
Definition: miscregs.hh:1449
Bitfield< 5 > t
Definition: miscregs.hh:1416
Bitfield< 15 > ide
Definition: miscregs.hh:1659
Bitfield< 21, 20 > fpen
Definition: miscregs.hh:1626
Bitfield< 0 > vm
Definition: miscregs.hh:1516
Bitfield< 9, 0 > res1_9_0_el2
Definition: miscregs.hh:1881
Bitfield< 3 > tcp3
Definition: miscregs.hh:1454
Bitfield< 9 > t9
Definition: miscregs.hh:1468
Bitfield< 18, 16 > ps
Definition: miscregs.hh:1735
#define BitUnion64(name)
Definition: bitunion.hh:362
Bitfield< 15 > nsasedis
Definition: miscregs.hh:1522
Bitfield< 15 > tid0
Definition: miscregs.hh:1501
MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition: miscregs.cc:132
Bitfield< 31 > l2rstDISABLE_monitor
Definition: miscregs.hh:1842
Bitfield< 6 > thee
Definition: miscregs.hh:1602
Bitfield< 9, 8 > rs
Definition: miscregs.hh:1594
Bitfield< 11 > cp11
Definition: miscregs.hh:1526
MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition: miscregs.cc:55
Bitfield< 4 > pd0
Definition: miscregs.hh:1712
Bitfield< 27 > nos3
Definition: miscregs.hh:1797
Bitfield< 23, 22 > rMode
Definition: miscregs.hh:1662
Bitfield< 3 > ufc
Definition: miscregs.hh:1651
Bitfield< 0 > tcp0
Definition: miscregs.hh:1457
Bitfield< 12 > tcp12
Definition: miscregs.hh:1444
Bitfield< 3 > ea
Definition: miscregs.hh:1552
Bitfield< 22 > a1
Definition: miscregs.hh:1722
Bitfield< 29, 0 > subArchDefined
Definition: miscregs.hh:1684
Bitfield< 15, 10 > it2
Definition: miscregs.hh:1408
Bitfield< 21, 20 > or2
Definition: miscregs.hh:1815
Bitfield< 1 > tcp1
Definition: miscregs.hh:1456
Bitfield< 20 > uwxn
Definition: miscregs.hh:1574
Bitfield< 12 > dc
Definition: miscregs.hh:1504
Bitfield< 20 > il
Definition: miscregs.hh:1406
Bitfield< 12 > tagRAMSlice
Definition: miscregs.hh:1835
Bitfield< 19 > dz
Definition: miscregs.hh:1576
Bitfield< 8 > sed
Definition: miscregs.hh:1596
Bitfield< 20 > tbi
Definition: miscregs.hh:1736
static const uint32_t FpscrQcMask
Definition: miscregs.hh:1679
Bitfield< 18 > tid3
Definition: miscregs.hh:1498
Bitfield< 11 > t11
Definition: miscregs.hh:1466
Bitfield< 27, 24 > cwg
Definition: miscregs.hh:1851
Bitfield< 6 > nEt
Definition: miscregs.hh:1549
Bitfield< 23 > epd1
Definition: miscregs.hh:1723
Bitfield< 38 > tbi1
Definition: miscregs.hh:1731
Bitfield< 11, 10 > ir5
Definition: miscregs.hh:1810
Bitfield< 4 > sa0
Definition: miscregs.hh:1606
Bitfield< 8 > vse
Definition: miscregs.hh:1508
Bitfield< 23, 20 > erg
Definition: miscregs.hh:1850

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