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types.hh File Reference

Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t. More...

#include <inttypes.h>
#include <cassert>
#include <memory>
#include <ostream>
#include <stdexcept>
#include "base/refcnt.hh"

Go to the source code of this file.

Classes

class  Cycles
 Cycles is a wrapper class for representing cycle counts, i.e. More...
 
struct  AtomicOpFunctor
 
struct  TypedAtomicOpFunctor< T >
 

Macros

#define ULL(N)   ((uint64_t)N##ULL)
 uint64_t constant More...
 
#define LL(N)   ((int64_t)N##LL)
 int64_t constant More...
 

Typedefs

typedef int64_t Counter
 Statistics counter type. More...
 
typedef uint64_t Tick
 Tick count type. More...
 
typedef uint64_t Addr
 Address type This will probably be moved somewhere else in the near future. More...
 
typedef uint16_t MicroPC
 
typedef int16_t ThreadID
 Thread index/ID type. More...
 
typedef int ContextID
 Globally unique thread context ID. More...
 
typedef int16_t PortID
 Port index/ID type, and a symbolic name for an invalid port id. More...
 
typedef std::shared_ptr< FaultBaseFault
 

Enumerations

enum  ByteOrder { BigEndianByteOrder, LittleEndianByteOrder }
 

Functions

static MicroPC romMicroPC (MicroPC upc)
 
static MicroPC normalMicroPC (MicroPC upc)
 
static bool isRomMicroPC (MicroPC upc)
 

Variables

const Tick MaxTick = ULL(0xffffffffffffffff)
 
static const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1)
 
const Addr MaxAddr = (Addr)-1
 
const ThreadID InvalidThreadID = (ThreadID)-1
 
const ContextID InvalidContextID = (ContextID)-1
 
const PortID InvalidPortID = (PortID)-1
 
decltype(nullptr) constexpr NoFault = nullptr
 

Detailed Description

Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.

Definition in file types.hh.

Macro Definition Documentation

◆ LL

#define LL (   N)    ((int64_t)N##LL)

◆ ULL

#define ULL (   N)    ((uint64_t)N##ULL)

uint64_t constant

Definition at line 50 of file types.hh.

Referenced by MipsISA::addHalfLsb(), AddrRange::AddrRange(), PosixKvmTimer::arm(), BiModeBP::BiModeBP(), ArmISA::FpOp::binaryOp(), LTAGE::bindex(), BiModeBP::btbUpdate(), TournamentBP::btbUpdate(), PosixKvmTimer::calcResolution(), AlphaISA::Interrupts::checkInterrupts(), RiscvISA::ISA::clear(), AlphaISA::Interrupts::clear(), SparcISA::Interrupts::clear(), ArmISA::Interrupts::clear(), SparcISA::ISA::clear(), ArmISA::ISA::clear64(), TsunamiCChip::clearDRIR(), TsunamiCChip::clearIPI(), TsunamiCChip::clearITI(), Linux::ThreadInfo::curThreadInfo(), TsunamiPChip::dmaAddr(), DRAMCtrl::DRAMCtrl(), AlphaISA::DTB_PTE_PPN(), EtherDump::dumpPacket(), Trie< Addr, uint32_t >::extendMask(), LTAGE::F(), findOverflow(), ArmISA::fixDest(), ArmISA::fixDivDest(), ArmISA::fixFpSFpDDest(), floorLog2(), ArmISA::flushToZero(), ArmISA::fpMaxNum(), ArmISA::fpMinNum(), ArmISA::fpMulAdd(), ArmISA::fpRecipEstimate(), ArmISA::fprSqrtEstimate(), Pl390::genSwiMask(), AlphaISA::Interrupts::getInterrupt(), SparcISA::getREDVector(), LTAGE::gindex(), AddrRange::granularity(), LTAGE::gtag(), X86ISA::I386Process::I386Process(), StatTest::init(), FreebsdArmSystem::initState(), SparcISA::PowerOnReset::invoke(), Iob::Iob(), ArmISA::isSnan(), AlphaISA::ITB_PTE_PPN(), LTAGE::lindex(), LTAGE::LTAGE(), SparcISA::TLB::MakeTsbPtr(), mask(), AlphaISA::PAddrIprSpace(), AlphaISA::Interrupts::post(), SparcISA::Interrupts::post(), ArmISA::Interrupts::post(), TsunamiCChip::postDRIR(), TsunamiCChip::postRTC(), AnnotateDumpCallback::process(), SparcISA::ISA::processHSTickCompare(), ComputeUnit::DataPort::processMemRespEvent(), ArmISA::FpOp::processNans(), SparcISA::ISA::processSTickCompare(), ArmISA::TableWalker::processWalkLPAE(), Pl390::readCpu(), PseudoInst::readfile(), SparcISA::ISA::readFSReg(), AlphaISA::ISA::readIpr(), X86ISA::Interrupts::readReg(), ArmSemihosting::readString(), TsunamiCChip::reqIPI(), StatTest::run(), IGbE::rxStateMachine(), iGbReg::TxdOp::setDd(), SparcISA::ISA::setFSReg(), AlphaISA::ISA::setIpr(), SparcISA::ISA::setMiscRegNoEffect(), X86ISA::Interrupts::setReg(), MipsISA::signExtend(), ArmISA::simd_modified_imm(), ArmISA::skipFunction(), Sparc32Process::Sparc32Process(), Sparc64Process::Sparc64Process(), IdeDisk::startDma(), AddrRange::stripes(), swap_byte64(), SparcISA::TLB::TagRead(), MipsISA::ProcessInfo::task(), X86ISA::ProcessInfo::task(), AlphaISA::ProcessInfo::task(), ArmISA::ProcessInfo::task(), ArmISA::FpOp::ternaryOp(), SparcISA::TlbEntry::TlbEntry(), TournamentBP::TournamentBP(), AlphaISA::TLB::translateData(), AlphaISA::TLB::translateInst(), TsunamiPChip::TsunamiPChip(), ArmISA::FpOp::unaryOp(), ArmISA::unsignedRecipEstimate(), ArmISA::unsignedRSqrtEstimate(), LTAGE::update(), LTAGE::FoldedHistory::update(), LTAGE::updateHistories(), AlphaISA::vtophys(), TsunamiCChip::write(), A9GlobalTimer::Timer::write(), Pl390::writeCpu(), and X86ISA::X86_64Process::X86_64Process().

Typedef Documentation

◆ Addr

typedef uint64_t Addr

Address type This will probably be moved somewhere else in the near future.

This should be at least as big as the biggest address width in use in the system, which will probably be 64 bits.

Definition at line 142 of file types.hh.

◆ ContextID

typedef int ContextID

Globally unique thread context ID.

Definition at line 175 of file types.hh.

◆ Counter

typedef int64_t Counter

Statistics counter type.

All counters are of 64-bit values.

Not much excuse for not using a 64-bit integer here, but if you're desperate and only run short simulations you could make this 32 bits.

Definition at line 58 of file types.hh.

◆ Fault

typedef std::shared_ptr<FaultBase> Fault

Definition at line 184 of file types.hh.

◆ MicroPC

typedef uint16_t MicroPC

Definition at line 144 of file types.hh.

◆ PortID

typedef int16_t PortID

Port index/ID type, and a symbolic name for an invalid port id.

Definition at line 181 of file types.hh.

◆ ThreadID

typedef int16_t ThreadID

Thread index/ID type.

Definition at line 171 of file types.hh.

◆ Tick

typedef uint64_t Tick

Tick count type.

Definition at line 63 of file types.hh.

Enumeration Type Documentation

◆ ByteOrder

enum ByteOrder
Enumerator
BigEndianByteOrder 
LittleEndianByteOrder 

Definition at line 204 of file types.hh.

Function Documentation

◆ isRomMicroPC()

static bool isRomMicroPC ( MicroPC  upc)
inlinestatic

◆ normalMicroPC()

static MicroPC normalMicroPC ( MicroPC  upc)
inlinestatic

Definition at line 155 of file types.hh.

References MicroPCRomBit.

Referenced by X86ISAInst::MicrocodeRom::fetchMicroop().

◆ romMicroPC()

static MicroPC romMicroPC ( MicroPC  upc)
inlinestatic

Definition at line 149 of file types.hh.

References MicroPCRomBit.

Referenced by X86ISA::X86FaultBase::invoke(), and X86ISA::InitInterrupt::invoke().

Variable Documentation

◆ InvalidContextID

const ContextID InvalidContextID = (ContextID)-1

◆ InvalidPortID

const PortID InvalidPortID = (PortID)-1

◆ InvalidThreadID

const ThreadID InvalidThreadID = (ThreadID)-1

◆ MaxAddr

const Addr MaxAddr = (Addr)-1

Definition at line 166 of file types.hh.

Referenced by AddrRange::getOffset(), and CacheBlk::invalidate().

◆ MaxTick

const Tick MaxTick = ULL(0xffffffffffffffff)

◆ MicroPCRomBit

const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1)
static

Definition at line 146 of file types.hh.

Referenced by isRomMicroPC(), normalMicroPC(), and romMicroPC().

◆ NoFault

decltype(nullptr) constexpr NoFault = nullptr

Definition at line 189 of file types.hh.

Referenced by X86ISA::RemoteGDB::acc(), ElasticTrace::addCommittedInst(), ElasticTrace::addSquashedInst(), TimingSimpleCPU::advanceInst(), BaseSimpleCPU::advancePC(), Checker< O3CPUImpl >::advancePC(), ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), RiscvISA::TLB::checkCacheability(), MipsISA::TLB::checkCacheability(), AlphaISA::TLB::checkCacheability(), PowerISA::TLB::checkCacheability(), BaseSimpleCPU::checkForInterrupts(), ArmISA::ArmStaticInst::checkForWFxTrap32(), ArmISA::ArmStaticInst::checkForWFxTrap64(), ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64(), ArmISA::TLB::checkPermissions(), ArmISA::TLB::checkPermissions64(), ArmISA::ArmStaticInst::checkSETENDEnabled(), LSQUnit< Impl >::checkViolations(), Minor::Execute::commit(), DefaultCommit< Impl >::commitHead(), Minor::Execute::commitInst(), DefaultCommit< Impl >::commitInsts(), TimingSimpleCPU::completeDataAccess(), TimingSimpleCPU::completeIfetch(), SimpleThread::copyArchRegs(), DefaultCommit< Impl >::DefaultCommit(), ArmISA::TableWalker::doL1Descriptor(), ArmISA::TableWalker::doL1DescriptorWrapper(), ArmISA::TableWalker::doL2Descriptor(), ArmISA::TableWalker::doL2DescriptorWrapper(), ArmISA::TableWalker::doLongDescriptor(), ArmISA::TableWalker::doLongDescriptorWrapper(), BaseKvmCPU::doMMIOAccess(), InstructionQueue< Impl >::doSquash(), Minor::Decode::evaluate(), SparcISA::Nop::execute(), SparcISA::WarnUnimplemented::execute(), WarnUnimplemented::execute(), McrMrcMiscInst::execute(), DefaultIEW< Impl >::executeInsts(), LSQUnit< Impl >::executeLoad(), Minor::Execute::executeMemRefInst(), LSQUnit< Impl >::executeStore(), DefaultFetch< Impl >::fetchCacheLine(), ArmISA::TableWalker::fetchDescriptor(), RiscvISA::TLB::finalizePhysical(), MipsISA::TLB::finalizePhysical(), X86ISA::TLB::finalizePhysical(), AlphaISA::TLB::finalizePhysical(), GenericTLB::finalizePhysical(), PowerISA::TLB::finalizePhysical(), SparcISA::TLB::finalizePhysical(), ArmISA::TLB::finalizePhysical(), ArmISA::Stage2MMU::Stage2Translation::finish(), ArmISA::Stage2LookUp::finish(), WholeTranslationState::finish(), DataTranslation< ExecContextPtr >::finish(), Minor::LSQ::SplitDataRequest::finish(), DefaultFetch< Impl >::finishTranslation(), TimingSimpleCPU::finishTranslation(), BaseDynInst< Impl >::finishTranslation(), WholeTranslationState::getFault(), SparcISA::Interrupts::getInterrupt(), X86ISA::Interrupts::getInterrupt(), ArmISA::TLB::getResultTe(), ArmISA::Stage2LookUp::getTe(), ArmISA::TLB::getTE(), DefaultCommit< Impl >::handleInterrupt(), Minor::Execute::handleMemResponse(), Minor::Fetch1::handleTLBResponse(), SimpleThread::hwrei(), BaseO3DynInst< Impl >::hwrei(), Minor::ExecContext::hwrei(), FullO3CPU< O3CPUImpl >::hwrei(), Minor::ExecContext::initiateMemRead(), TimingSimpleCPU::initiateMemRead(), BaseDynInst< Impl >::initiateMemRead(), BaseDynInst< Impl >::initiateTranslation(), BaseDynInst< Impl >::initVars(), RiscvISA::SyscallFault::invoke_se(), DefaultCommit< Impl >::isDrained(), Minor::ForwardLineData::isFault(), Minor::MinorDynInst::isFault(), Minor::LSQ::LSQRequest::makePacket(), ArmISA::Stage2LookUp::mergeTe(), Minor::Fetch1::minorTraceResponseLine(), FullO3CPU< O3CPUImpl >::processInterrupts(), Minor::Fetch1::processResponse(), ArmISA::TableWalker::processWalkWrapper(), DefaultCommit< Impl >::propagateInterrupt(), LSQUnit< Impl >::read(), ArmISA::Stage2MMU::readDataUntimed(), AtomicSimpleCPU::readMem(), CheckerCPU::readMem(), readMemAtomic(), X86ISA::readMemAtomic(), Trace::TarmacParserRecord::readMemNoEffect(), X86ISA::readPackedMemAtomic(), X86ISA::Walker::WalkerState::recvPacket(), Minor::ForwardLineData::reportData(), Minor::LSQ::SplitDataRequest::retireResponse(), TimingSimpleCPU::sendFetch(), ArmISA::ISA::setMiscReg(), WholeTranslationState::setNoFault(), X86ISA::Walker::start(), X86ISA::Walker::WalkerState::startFunctional(), X86ISA::Walker::WalkerState::startWalk(), X86ISA::Walker::WalkerState::stepWalk(), Minor::Execute::takeInterrupt(), ArmISA::TLB::testTranslation(), ArmISA::TLB::testWalk(), AtomicSimpleCPU::tick(), X86ISA::TLB::translate(), EmulationPageTable::translate(), X86ISA::GpuTLB::translate(), GenericTLB::translateAtomic(), ArmISA::TLB::translateComplete(), RiscvISA::TLB::translateData(), MipsISA::TLB::translateData(), SparcISA::TLB::translateData(), PowerISA::TLB::translateData(), ArmISA::TLB::translateFs(), RiscvISA::TLB::translateInst(), MipsISA::TLB::translateInst(), AlphaISA::TLB::translateInst(), SparcISA::TLB::translateInst(), PowerISA::TLB::translateInst(), X86ISA::TLB::translateInt(), X86ISA::GpuTLB::translateInt(), ArmISA::ArmStaticInst::trapWFx(), try_translate(), Minor::Execute::tryToBranch(), Minor::Fetch1::tryToSendToTransfers(), Minor::LSQ::tryToSendToTransfers(), ArmISA::ArmStaticInst::undefinedFault64(), Checker< O3CPUImpl >::validateState(), Checker< O3CPUImpl >::verify(), X86ISA::vtophys(), ArmISA::TableWalker::walk(), WholeTranslationState::WholeTranslationState(), LSQUnit< Impl >::write(), LSQUnit< Impl >::writeback(), DefaultIEW< Impl >::writebackInsts(), Minor::ExecContext::writeMem(), AtomicSimpleCPU::writeMem(), TimingSimpleCPU::writeMem(), BaseDynInst< Impl >::writeMem(), CheckerCPU::writeMem(), writeMemAtomic(), X86ISA::writeMemAtomic(), and BaseDynInst< Impl >::~BaseDynInst().


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