Public Types | Public Member Functions | Static Public Member Functions | Protected Attributes | Private Types | Private Attributes | Static Private Attributes | List of all members
SimObject Class Reference

Abstract superclass for simulation objects. More...

#include <sim_object.hh>

Inheritance diagram for SimObject:
EventManager Serializable Drainable AbstractNVM AbstractReplacementPolicy AlphaISA::Interrupts AlphaISA::ISA ArmISA::Interrupts ArmISA::ISA ArmISA::PMU ArmISA::Stage2MMU ArmSemihosting BaseMemProbe BaseReplacementPolicy BaseTLB BasicLink BPredUnit CacheMemory ClockDomain ClockedObject DirectedGenerator DirectoryMemory DiskImage DVFSHandler EmulatedDriver EtherDump EtherObject FaultModel FUDesc FUPool Gicv2mFrame GoodbyeObject HelloObject I2CDevice IdeDisk IntrControl KvmVM MemChecker MessageBuffer MinorFU MinorFUPool MinorFUTiming MinorOpClass MinorOpClassSet MipsISA::Interrupts MipsISA::ISA OpDesc Platform PowerISA::Interrupts PowerISA::ISA PowerModel PowerModelState Prefetcher ProbeListenerObject Process PS2Device RealViewTemperatureSensor RiscvISA::Interrupts RiscvISA::ISA Root SerialDevice SimpleDisk SimpleObject SnoopFilter SouthBridge SparcISA::Interrupts SparcISA::ISA SubSystem ThermalCapacitor ThermalDomain ThermalNode ThermalReference ThermalResistor TimingExpr Trace::InstTracer UFSHostDevice::UFSSCSIDevice VectorRegisterFile VirtIODeviceBase VncInput VoltageDomain Wavefront WireBuffer X86ISA::ACPI::RSDP X86ISA::ACPI::SysDescTable X86ISA::E820Entry X86ISA::E820Table X86ISA::IntelMP::BaseConfigEntry X86ISA::IntelMP::ConfigTable X86ISA::IntelMP::ExtConfigEntry X86ISA::IntelMP::FloatingPointer X86ISA::IntLine X86ISA::IntSinkPin X86ISA::IntSourcePin X86ISA::ISA X86ISA::SMBios::SMBiosStructure X86ISA::SMBios::SMBiosTable

Public Types

typedef SimObjectParams Params

Public Member Functions

const Paramsparams () const
 SimObject (const Params *_params)
virtual ~SimObject ()
virtual const std::string name () const
virtual void init ()
 init() is called after all C++ SimObjects have been created and all ports are connected. More...
virtual void loadState (CheckpointIn &cp)
 loadState() is called on each SimObject when restoring from a checkpoint. More...
virtual void initState ()
 initState() is called on each SimObject when not restoring from a checkpoint. More...
virtual void regStats ()
 Register statistics for this object. More...
virtual void resetStats ()
 Reset statistics associated with this object. More...
virtual void regProbePoints ()
 Register probe points for this object. More...
virtual void regProbeListeners ()
 Register probe listeners for this object. More...
ProbeManagergetProbeManager ()
 Get the probe manager for this object. More...
virtual void startup ()
 startup() is the final initialization call before simulation. More...
DrainState drain () override
 Provide a default implementation of the drain interface for objects that don't need draining. More...
virtual void memWriteback ()
 Write back dirty buffers to memory using functional writes. More...
virtual void memInvalidate ()
 Invalidate the contents of memory buffers. More...
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
- Public Member Functions inherited from EventManager
 EventManager (EventManager &em)
 EventManager (EventManager *em)
 EventManager (EventQueue *eq)
EventQueueeventQueue () const
void schedule (Event &event, Tick when)
void deschedule (Event &event)
void reschedule (Event &event, Tick when, bool always=false)
void schedule (Event *event, Tick when)
void deschedule (Event *event)
void reschedule (Event *event, Tick when, bool always=false)
void wakeupEventQueue (Tick when=(Tick) -1)
void setCurTick (Tick newVal)
- Public Member Functions inherited from Serializable
 Serializable ()
virtual ~Serializable ()
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section. More...
void serializeSection (CheckpointOut &cp, const std::string &name) const
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object. More...
void unserializeSection (CheckpointIn &cp, const std::string &name)
- Public Member Functions inherited from Drainable
DrainState drainState () const
 Return the current drain state of an object. More...
virtual void notifyFork ()
 Notify a child process of a fork. More...

Static Public Member Functions

static void serializeAll (CheckpointOut &cp)
 Serialize all SimObjects in the system. More...
static SimObjectfind (const char *name)
 Find the SimObject with the given name and return a pointer to it. More...
- Static Public Member Functions inherited from Serializable
static const std::string & currentSection ()
 Get the fully-qualified name of the active section. More...
static void serializeAll (const std::string &cpt_dir)
static void unserializeGlobals (CheckpointIn &cp)

Protected Attributes

const SimObjectParams * _params
 Cached copy of the object parameters. More...
- Protected Attributes inherited from EventManager
 A pointer to this object's event queue. More...

Private Types

typedef std::vector< SimObject * > SimObjectList

Private Attributes

 Manager coordinates hooking up probe points with listeners. More...

Static Private Attributes

static SimObjectList simObjectList
 List of all instantiated simulation objects. More...

Additional Inherited Members

- Static Public Attributes inherited from Serializable
static int ckptCount = 0
static int ckptMaxCount = 0
static int ckptPrevCount = -1
- Protected Member Functions inherited from Drainable
 Drainable ()
virtual ~Drainable ()
virtual void drainResume ()
 Resume execution after a successful drain. More...
void signalDrainDone () const
 Signal that an object is drained. More...

Detailed Description

Abstract superclass for simulation objects.

Represents things that correspond to physical components and can be specified via the config file (CPUs, caches, etc.).

SimObject initialization is controlled by the instantiate method in src/python/m5/ There are slightly different initialization paths when starting the simulation afresh and when loading from a checkpoint. After instantiation and connecting ports, initializes the object using the following call sequence:

  1. SimObject::init()
  2. SimObject::regStats()
  3. SimObject::resetStats()
  4. SimObject::startup()
  5. Drainable::drainResume() if resuming from a checkpoint.
Whenever a method is called on all objects in the simulator's object tree (e.g., init(), startup(), or loadState()), a pre-order depth-first traversal is performed (see descendants() in This has the effect of calling the method on the parent node before its children.

Definition at line 94 of file sim_object.hh.

Member Typedef Documentation

◆ Params

typedef SimObjectParams SimObject::Params

Definition at line 110 of file sim_object.hh.

◆ SimObjectList

Definition at line 97 of file sim_object.hh.

Constructor & Destructor Documentation

◆ SimObject()

SimObject::SimObject ( const Params _params)

Definition at line 58 of file

References probeManager, and simObjectList.

Referenced by params().

◆ ~SimObject()

SimObject::~SimObject ( )

Definition at line 68 of file

References probeManager.

Referenced by params().

Member Function Documentation

◆ drain()

DrainState SimObject::drain ( )

Provide a default implementation of the drain interface for objects that don't need draining.

Implements Drainable.

Definition at line 184 of file sim_object.hh.

References Drained.

◆ find()

SimObject * SimObject::find ( const char *  name)

Find the SimObject with the given name and return a pointer to it.

Primarily used for interactive debugging. Argument is char* rather than std::string to make it callable from gdb.

Definition at line 179 of file

References ArmISA::i, name(), and simObjectList.

Referenced by DVFSHandler::findDomain(), and unserialize().

◆ getProbeManager()

ProbeManager * SimObject::getProbeManager ( )

◆ init()

void SimObject::init ( )

◆ initState()

void SimObject::initState ( )

◆ loadState()

void SimObject::loadState ( CheckpointIn cp)

loadState() is called on each SimObject when restoring from a checkpoint.

The default implementation simply calls unserialize() if there is a corresponding section in the checkpoint. However, objects can override loadState() to get other behaviors, e.g., doing other programmed initializations after unserialize(), or complaining if no checkpoint section is found.

cpCheckpoint to restore the state from.

Definition at line 79 of file

References DPRINTF, name(), CheckpointIn::sectionExists(), and Serializable::unserializeSection().

Referenced by name().

◆ memInvalidate()

virtual void SimObject::memInvalidate ( )

Invalidate the contents of memory buffers.

When the switching to hardware virtualized CPU models, we need to make sure that we don't have any cached state in the system that might become stale when we return. This method is used to flush all such state back to main memory.

This does not cause any dirty state to be written back to memory.

Reimplemented in Cache, BaseCache, and BaseTLB.

Definition at line 207 of file sim_object.hh.

◆ memWriteback()

virtual void SimObject::memWriteback ( )

Write back dirty buffers to memory using functional writes.

After returning, an object implementing this method should have written all its dirty data back to memory. This method is typically used to prepare a system with caches for checkpointing.

Reimplemented in Cache, BaseCache, and RubySystem.

Definition at line 194 of file sim_object.hh.

◆ name()

virtual const std::string SimObject::name ( ) const

Reimplemented in ElasticTrace, and SimpleTrace.

Definition at line 117 of file sim_object.hh.

References getProbeManager(), init(), initState(), loadState(), params(), regProbeListeners(), regProbePoints(), regStats(), resetStats(), and startup().

Referenced by Terminal::accept(), VncServer::accept(), Cache::access(), ArmISA::PMU::addEventProbe(), CxxConfigManager::bindMasterPort(), CxxConfigManager::bindPort(), Cache::Cache(), NetworkInterface::calculateVC(), DVFSHandler::clkPeriodAtPerfLevel(), SrcClockDomain::clockPeriod(), RealViewOsc::clockPeriod(), CoherentXBar::CoherentXBar(), CommMonitor::CommMonitor(), MemTest::completeRequest(), connectPorts(), Sinic::Base::cpuIntrPost(), NSGigE::cpuIntrPost(), CpuLocalTimer::CpuLocalTimer(), Sinic::Device::Device(), DistEtherLink::DistEtherLink(), Pl111::dmaDone(), DRAMCtrl::DRAMCtrl(), DRAMSim2::DRAMSim2(), FUPool::dump(), DVFSHandler::DVFSHandler(), IdeController::EndBitUnion(), EnergyCtrl::EnergyCtrl(), MessageBuffer::enqueue(), EtherLink::EtherLink(), EtherSwitch::EtherSwitch(), find(), FlashDevice::FlashDevice(), Cache::functionalAccess(), GarnetSyntheticTraffic::GarnetSyntheticTraffic(), GenericTimerMem::GenericTimerMem(), System::getMasterId(), MemObject::getMasterPort(), ComputeUnit::getMasterPort(), MemObject::getSlavePort(), GoodbyeObject::GoodbyeObject(), GpuDispatcher::GpuDispatcher(), X86ISA::GpuTLB::GpuTLB(), Cache::handleFill(), SimpleCache::handleRequest(), Cache::handleSnoop(), HDLcd::HDLcd(), HelloObject::HelloObject(), CPA::hwWe(), IdeDisk::IdeDisk(), IGbE::IGbE(), FetchStage::init(), LocalMemPipeline::init(), ScheduleStage::init(), GlobalMemPipeline::init(), ScoreboardCheckStage::init(), ExecStage::init(), System::init(), PioDevice::init(), ExternalMaster::init(), ExternalSlave::init(), DmaDevice::init(), DRAMSim2::init(), TrafficGen::init(), CoherentXBar::init(), BaseCache::init(), DRAMCtrl::init(), Process::initState(), X86ISA::Interrupts::Interrupts(), LinuxArmSystem::LinuxArmSystem(), Terminal::listen(), VncServer::listen(), loadState(), MathExprPowerModel::MathExprPowerModel(), MemTest::MemTest(), MemTraceProbe::MemTraceProbe(), SimpleTrace::name(), CopyEngine::CopyEngineChannel::name(), PciHost::DeviceInterface::name(), ElasticTrace::name(), BaseRemoteGDB::name(), BaseXBar::Layer< MasterPort, SlavePort >::name(), X86ISA::Walker::WalkerState::name(), DRAMCtrl::Rank::name(), ArmISA::TableWalker::WalkerState::name(), NoncoherentXBar::NoncoherentXBar(), TrafficGen::noProgress(), MemTest::noRequest(), MemTest::noResponse(), NSGigE::NSGigE(), TrafficGen::parseConfig(), VoltageDomain::perfLevel(), SrcClockDomain::perfLevel(), Pl011::Pl011(), PL031::PL031(), Pl111::Pl111(), SimpleExtLink::print(), BasicRouter::print(), BasicLink::print(), GarnetIntLink::print(), SimpleIntLink::print(), GarnetExtLink::print(), Prefetcher::print(), MessageBuffer::print(), CacheMemory::print(), System::printSystems(), Linux::DebugPrintkEvent::process(), AnnotateDumpCallback::process(), TLBCoalescer::processProbeTLBEvent(), ClockedObject::pwrState(), HDLcd::pxlFrameDone(), IsaFake::read(), UFSHostDevice::readCallback(), PciDevice::readConfig(), UFSHostDevice::readDevice(), IdeDisk::readDisk(), CacheMemory::recordCacheContents(), NoncoherentXBar::recvAtomic(), CoherentXBar::recvAtomic(), CoherentXBar::recvAtomicSnoop(), DRAMCtrl::MemoryPort::recvFunctional(), NoncoherentXBar::recvFunctional(), SimpleMemory::recvFunctional(), SerialLink::SerialLinkSlavePort::recvFunctional(), DRAMSim2::recvFunctional(), Bridge::BridgeSlavePort::recvFunctional(), CoherentXBar::recvFunctional(), CoherentXBar::recvFunctionalSnoop(), MemCheckerMonitor::recvTimingResp(), AddrMapper::recvTimingResp(), Cache::recvTimingResp(), CoherentXBar::recvTimingSnoopReq(), StackDistProbe::regStats(), SimpleNetwork::regStats(), MemFootprintProbe::regStats(), Sequencer::regStats(), EtherDevice::regStats(), Switch::regStats(), RubySystem::regStats(), MemTest::regStats(), BPredUnit::regStats(), CommMonitor::regStats(), PowerModelState::regStats(), AlphaISA::TLB::regStats(), ThermalDomain::regStats(), AbstractController::regStats(), HDLcd::regStats(), Router::regStats(), GarnetNetwork::regStats(), GPUCoalescer::regStats(), RiscvISA::TLB::regStats(), Prefetcher::regStats(), MipsISA::TLB::regStats(), Process::regStats(), ClockDomain::regStats(), MessageBuffer::regStats(), QueuedPrefetcher::regStats(), CacheMemory::regStats(), VoltageDomain::regStats(), PowerModel::regStats(), BasePrefetcher::regStats(), TLBCoalescer::regStats(), FALRU::regStats(), FlashDevice::regStats(), X86ISA::TLB::regStats(), BaseTags::regStats(), PowerISA::TLB::regStats(), SnoopFilter::regStats(), X86ISA::GpuTLB::regStats(), TrafficGen::regStats(), ClockedObject::regStats(), IdeDisk::regStats(), Sinic::Device::regStats(), AbstractMemory::regStats(), SimpleCache::regStats(), Wavefront::regStats(), System::regStats(), ArmISA::TLB::regStats(), ComputeUnit::regStats(), CoherentXBar::regStats(), BaseCache::regStats(), UFSHostDevice::regStats(), UFSHostDevice::requestHandler(), TrafficGen::resolveFile(), Root::Root(), RubyDirectedTester::RubyDirectedTester(), RubyPort::RubyPort(), RubyTester::RubyTester(), VoltageDomain::sanitiseVoltages(), RubySystem::serialize(), CowDiskImage::serialize(), serializeAll(), WireBuffer::setDescription(), ConditionRegisterState::setParent(), VecRegisterState::setParent(), LdsState::setParent(), ArmISA::TLB::setTestInterface(), SimpleCache::SimpleCache(), SimpleMemory::SimpleMemory(), SrcClockDomain::SrcClockDomain(), MemTraceProbe::startup(), LinuxArmSystem::startup(), VoltageDomain::startup(), ArmISA::TableWalker::TableWalker(), ThermalModel::ThermalModel(), GarnetSyntheticTraffic::tick(), MemTest::tick(), TLBCoalescer::TLBCoalescer(), TrafficGen::TrafficGen(), DrainManager::tryDrain(), RubyPort::trySendRetries(), UFSHostDevice::UFSHostDevice(), Sinic::Base::unserialize(), unserialize(), NSGigE::unserialize(), TrafficGen::update(), DerivedClockDomain::updateClockPeriod(), VncInput::VncInput(), VoltageDomain::voltage(), DVFSHandler::voltageAtPerfLevel(), VoltageDomain::VoltageDomain(), IsaFake::write(), PciDevice::writeConfig(), UFSHostDevice::writeDevice(), IdeDisk::writeDisk(), and SimObjectResolver::~SimObjectResolver().

◆ params()

const Params* SimObject::params ( ) const

◆ regProbeListeners()

void SimObject::regProbeListeners ( )

Register probe listeners for this object.

No probe listeners by default, so do nothing in base.

Reimplemented in ArmISA::PMU, ElasticTrace, SimPoint, BaseMemProbe, and SimpleTrace.

Definition at line 126 of file

Referenced by CxxConfigManager::instantiate(), and name().

◆ regProbePoints()

void SimObject::regProbePoints ( )

Register probe points for this object.

No probe points by default, so do nothing in base.

Reimplemented in ArmISA::TLB, PowerModel, CommMonitor, and BPredUnit.

Definition at line 118 of file

Referenced by CxxConfigManager::instantiate(), name(), and PowerModel::regStats().

◆ regStats()

void SimObject::regStats ( )

◆ resetStats()

void SimObject::resetStats ( )

Reset statistics associated with this object.

Reimplemented in Sinic::Device, GPUCoalescer, Router, AbstractController, RubySystem, NetworkLink, Switch, and Sequencer.

Definition at line 110 of file

Referenced by DRAMCtrl::Rank::forceSelfRefreshExit(), name(), and Sinic::Device::resetStats().

◆ serialize()

void SimObject::serialize ( CheckpointOut cp) const

Serialize an object.

Output an object's state into the current checkpoint section.

cpCheckpoint state

Implements Serializable.

Reimplemented in System, TickedObject, and VoltageDomain.

Definition at line 209 of file sim_object.hh.

Referenced by SrcClockDomain::clkPeriodAtPerfLevel(), and SrcClockDomain::serialize().

◆ serializeAll()

void SimObject::serializeAll ( CheckpointOut cp)

Serialize all SimObjects in the system.

Definition at line 140 of file

References ArmISA::i, ObjectMatch::match(), name(), Serializable::serializeSection(), and simObjectList.

Referenced by Serializable::serializeAll(), and unserialize().

◆ startup()

void SimObject::startup ( )

◆ unserialize()

void SimObject::unserialize ( CheckpointIn cp)

Unserialize an object.

Read an object's state from the current checkpoint section.

cpCheckpoint state

Implements Serializable.

Reimplemented in System, TickedObject, and VoltageDomain.

Definition at line 210 of file sim_object.hh.

References find(), name(), and serializeAll().

Referenced by SrcClockDomain::clkPeriodAtPerfLevel(), and SrcClockDomain::unserialize().

Member Data Documentation

◆ _params

const SimObjectParams* SimObject::_params

Cached copy of the object parameters.

Definition at line 107 of file sim_object.hh.

Referenced by BasicRouter::params(), SimpleExtLink::params(), BasicLink::params(), X86ISA::I8237::params(), RiscvISA::Interrupts::params(), PowerISA::Interrupts::params(), MipsISA::Interrupts::params(), EtherObject::params(), MmDisk::params(), BadDevice::params(), DumbTOD::params(), EtherSwitch::params(), BaseGic::params(), FaultModel::params(), EtherDevice::params(), Uart::params(), MemCheckerMonitor::params(), AmbaFake::params(), X86ISA::Speaker::params(), IsaFake::params(), MemObject::params(), AlphaISA::Interrupts::params(), SparcISA::Interrupts::params(), X86ISA::ISA::params(), SimpleIntLink::params(), EtherBus::params(), EtherTapBase::params(), TsunamiPChip::params(), RealView::params(), CommMonitor::params(), BasicExtLink::params(), X86ISA::I8254::params(), ArmISA::Interrupts::params(), Network::params(), Sinic::Base::params(), BasicIntLink::params(), MaltaCChip::params(), Uart8250::params(), X86ISA::I8259::params(), X86ISA::I82094AA::params(), TsunamiCChip::params(), Root::params(), Trace::ArmNativeTrace::params(), PL031::params(), AlphaBackdoor::params(), params(), MaltaIO::params(), TsunamiIO::params(), X86ISA::I8042::params(), RiscvISA::ISA::params(), Iob::params(), PowerISA::ISA::params(), AlphaISA::ISA::params(), Sp804::params(), MipsISA::ISA::params(), IdeController::params(), EtherDevBase::params(), EtherTapStub::params(), A9GlobalTimer::params(), EtherLink::params(), RealViewCtrl::params(), CpuLocalTimer::params(), CopyEngine::params(), X86ISA::Interrupts::params(), VGic::params(), X86ISA::Walker::params(), DistEtherLink::params(), SparcISA::ISA::params(), Pl390::params(), Pl111::params(), IGbE::params(), ArmISA::ISA::params(), and ArmISA::TableWalker::params().

◆ probeManager

ProbeManager* SimObject::probeManager

Manager coordinates hooking up probe points with listeners.

Definition at line 103 of file sim_object.hh.

Referenced by getProbeManager(), SimObject(), and ~SimObject().

◆ simObjectList

SimObject::SimObjectList SimObject::simObjectList

List of all instantiated simulation objects.

Definition at line 100 of file sim_object.hh.

Referenced by find(), serializeAll(), and SimObject().

The documentation for this class was generated from the following files:

Generated on Fri Apr 20 2018 09:05:09 for gem5 by doxygen 1.8.13