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<div style="font-size:202%;border:none;margin: 0;padding:.1em;text-align:center;color:#000">The M5 Simulator System</div>
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<div style="font-size:140%;border:none;margin: 0;padding:.1em;text-align:center;color:#000">A modular platform for computer system architecture research</div>
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<div style="font-size:202%;border:none;margin: 0;padding:.3em;text-align:center;color:#000">The gem5 Simulator</div>
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<div style="font-size:140%;border:none;margin: 0;padding:.3em;text-align:center;color:#000">A modular platform for computer-system architecture research</div>
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===About===
 
===About===
* M5 is a modular platform for computer system architecture research, encompassing system-level architecture as well as processor microarchitecture.
+
* The gem5 simulator is a modular platform for computer-system architecture research, encompassing system-level architecture as well as processor microarchitecture.
 +
 
 +
===Key features===
 +
 
 +
* ''Multiple interchangeable CPU models.'' gem5 provides four interpretation-based CPU models: a simple one-CPI CPU; a detailed model of an in-order CPU, and a detailed model of an out-of-order CPU. These CPU models use a common high-level ISA description. In addition, gem5 features a KVM-based CPU that uses virtualisation to accelerate simulation.
 +
 
 +
* ''[[GPU_Models|A fully integrated GPU]]'' model that executes real machine ISA and supports shared virtual memory with the host CPU.
  
===News===
+
* ''[[Media:2015_ws_04_ISCA_2015_NoMali.pdf|A NoMali GPU model.]] '' gem5 comes with an integrated NoMali GPU model that is compatible with the Linux and Android GPU driver stack, and thus removes the need for software rendering. The NoMali GPU does not produce any output, but ensures that CPU-centric experiments produce representative results.
* [[2009-02-09]] - The development repository has moved the minimum version of SCons required to 0.98.1. Please let us know if this causes major headaches.
 
* [[2008-10-15]] - We've added a page on [[Adding Functionality]] while preserving the ability to update to new versions of M5.
 
* [[2008-10-08]] - <b>M5 2.0b6 released</b> on the [[Download]] page.
 
* [[2008-06-13]] - <b>M5 [[Repository]] is open to the public</b>
 
  
=== Download ===
+
* ''[[Media:2015_ws_02_hansson_gem5_workshop_2015.pdf|Event-driven memory system.]]'' gem5 features a detailed, event-driven memory system including caches, crossbars, snoop filters, and a fast and accurate DRAM controller model, for capturing the impact of current and emerging memories, e.g. LPDDR3/4/5, DDR3/4, GDDR5, HBM1/2/3, HMC, WideIO1/2. The components can be arranged flexibly, e.g., to model complex multi-level non-uniform cache hierarchies with heterogeneous memories.
* The current public release of M5 is available at http://repo.m5sim.org. (See the [[Repository]] page for details.)  Auxiliary files are available on on our [[Download]] page. Please look at the sidebar for links to file bugs and for mailing list subscription information.  
 
  
===Key features===
+
* ''[[TraceCPU|A trace-based CPU]]'' model that plays back elastic traces, which are dependency and timing annotated traces generated by a probe attached to the out-of-order CPU model. The focus of the Trace CPU model is to achieve memory-system (cache-hierarchy, interconnects and main memory) performance exploration in a fast and reasonably accurate way instead of using the detailed CPU model.
* ''Pervasive object orientation.'' Major simulation structures (CPUs, busses, caches, etc.) are represented as objects, both externally and internally. M5's configuration language allows flexible composition of these objects to describe complex simulation targets, e.g., multi-system networks where each system comprises multiple CPUs and a hierarchy of caches. M5's internal object orientation (using C++) provides in addition to the usual software engineering advantages.
 
  
* ''Multiple interchangeable CPU models.'' M5 currently provides three interchangeable CPU objects: a simple, functional, one-CPI CPU; a detailed model of an out-of-order SMT-capable CPU; and a random memory-system tester. The first two models use a common high-level ISA description.
+
* ''Homogeneous and heterogeneous multi-core.'' The CPU models and caches can be combined in arbitrary topologies, creating homogeneous, and heterogeneous multi-core systems. A MOESI snooping cache coherence protocol keeps the caches coherent.
  
* ''Event-driven memory system.'' M5 features a detailed, event-driven memory system including non-blocking caches and split-transaction busses. These components can be arranged flexibly, e.g., to model complex multi-level cache hierarchies. The caches support a separable coherence policy module; M5 currently includes a simple snooping cache coherence protocol.
+
* ''Multiple ISA support.''  gem5 decouples ISA semantics from its CPU models, enabling effective support of multiple ISAs.  Currently gem5 supports the Alpha, ARM, SPARC, MIPS, POWER, RISC-V and x86 ISAs. See [[Supported Architectures]] for more information.
* ''Multiple ISA support.''  M5 decouples ISA semantics from its timing CPU models, enabling effective support of multiple ISAs.  M5 currently supports the Alpha, SPARC, MIPS, and ARM ISAs, with x86 support in progress. See [[Supported Architectures]] for more information.
 
 
* ''Full-system capability.''
 
* ''Full-system capability.''
** '''Alpha''': M5 models a DEC Tsunami system in sufficient detail to boot unmodified Linux 2.4/2.6, FreeBSD, or L4Ka::Pistachio. We have also booted HP/Compaq's Tru64 5.1 operating system in the past, though we no longer actively maintain that capability.
+
** '''Alpha''': gem5 models a DEC Tsunami system in sufficient detail to boot unmodified Linux 2.4/2.6, FreeBSD, or L4Ka::Pistachio. We have also booted HP/Compaq's Tru64 5.1 operating system in the past, though we no longer actively maintain that capability.
** '''SPARC''': M5 models a single core of a UltraSPARC T1 processor with sufficient detail to boot Solaris in a similar manner as the Sun T1 Architecture simulator tools (building the hypervisor with specific defines and using the HSMID virtual disk driver).
+
** '''ARM''': gem5 can model up to 64 (heterogeneous) cores of a Realview ARM platform, and boot [[ARM_Linux_Kernel|unmodified Linux]] and [[Android_Marshmallow|Android]] with a combination of in-order and out-of-order CPUs. The ARM implementation supports 32 or 64-bit kernels and applications.  
** '''MIPS/ARM/x86''': In progress
+
** '''SPARC''': The gem5 simulator models a single core of a UltraSPARC T1 processor with sufficient detail to boot Solaris in a similar manner as the Sun T1 Architecture simulator tools (building the hypervisor with specific defines and using the HSMID virtual disk driver).
* ''Multiprocessor / multi-system capability.'' Thanks to M5's object orientation, instantiation of multiple CPU objects within a system is trivial. Combined with the snooping bus-based coherence protocol supported by the caches, M5 can model symmetric multiprocessor systems. Because a complete system is just a collection of objects (CPUs, caches, memory, etc.), multiple systems can be instantiated within a single simulation process. In conjunction with full-system modeling, this feature allows simulation of entire client-server networks.
+
** '''x86''': The gem5 simulator supports a standard PC platform
 +
 
 +
* ''Multi-system capability.'' Multiple systems can be instantiated within a single simulation process. In conjunction with full-system modeling, this feature allows simulation of entire client-server networks.
 +
 
 +
* ''Power and energy modeling.'' gem5’s objects are arranged in OS-visible power and clock domains, enabling a range of experiments in power- and energy-efficiency. With out-of-the-box support for OS-controller Dynamic Voltage and Frequency (DVFS) scaling, gem5 provides a complete platform for research in future energy-efficient systems. See [[Running_gem5#Experimenting_with_DVFS|how to run your own DVFS experiments]].
 +
 
 +
* ''[[Media:2015_ws_09_2015-06-14_Gem5_ISCA.pptx|Co-simulation with SystemC.]]'' gem5 can be included in a SystemC simulation, effectively running as a thread inside the SystemC event kernel, and keeping the events and timelines synchronized between the two worlds. This functionality enables the gem5 components to interoperate with a wide range of System on Chip (SoC) component models, such as interconnects, devices and accelerators. A wrapper for SystemC Transaction Level Modelling (TLM) is provided.
 +
 
 +
=== Download ===
 +
* The canonical version of gem5 is available at https://gem5.googlesource.com/.  (See the [[Repository]] page for details.)  Auxiliary files are available on on our [[Download]] page.  
  
 
===Additional details===
 
===Additional details===
  
* ''Application-only support.'' In application-only (non-full-system) mode, M5 can execute a variety of architecture/OS binaries with OS emulation or SimpleScalar Alpha EIO trace files.
+
* ''Application-only support.'' In application-only (non-full-system) mode, gem5 can execute a variety of architecture/OS binaries with Linux emulation.
 
 
* ''Platforms.'' M5 runs on most operating systems (Linux, MacOS X, Solaris, OpenBSD, Cygwin) and architectures (x86, x86-64, SPARC, Alpha, and PPC). However, all guest platforms aren't supported on all host platforms (most notably Alpha requires little-endian hardware). It is readily portable to other hosts and other Unix-like operating systems that are supported by GCC. Alpha binaries to run on M5 (including the full Linux kernel) can be built on x86 systems using gcc-based cross-compilation tools, so no Alpha hardware is needed to make full use of M5.
 
  
* ''Licensing.'' M5 is being released under a Berkeley-style open source license. Roughly speaking, you are free to use our code however you wish, as long as you leave our copyright on it. For more details, see the LICENSE file included in the source download. Note that the portions of M5 derived from other sources are also subject to the licensing restrictions of the original sources (notably SimpleScalar).
+
* ''Platforms.'' The gem5 simulator runs on most operating systems (Linux, MacOS X, OpenBSD) and architectures (x86, x86-64, ARM, SPARC, Alpha, and PPC). However, all guest platforms aren't supported on all host platforms (most notably Alpha requires little-endian hardware). It is readily portable to other hosts and other Unix-like operating systems that are supported by GCC and/or clang.
  
* ''Provenance.'' Portions of M5 (EIO trace support and parts of our old obsolete detailed CPU model) were derived from SimpleScalar. These portions are released separately under the SimpleScalar license. We have a new detailed CPU model that eliminates any need for the SimpleScalar code unless you use EIO traces. We are also grateful to the SimOS and SimOS/Alpha developers, as SimOS/Alpha was an invaluable reference platform during our development of full-system mode.
+
* ''Licensing.'' The gem5 simulator is released under a Berkeley-style open source license. Roughly speaking, you are free to use our code however you wish, as long as you leave our copyright on it. For more details, see the LICENSE file included in the source download. Note that the portions of gem5 derived from other sources are also subject to the licensing restrictions of the original sources.
  
 
===Documentation===
 
===Documentation===
  
There are several sources of documentation for M5:
+
There are several sources of documentation for gem5:
  
 
* The most detailed and up-to-date documentation is on this wiki.  The [[documentation]] page serves as a general table of contents for these pages.  There is also a list of [[Frequently Asked Questions]].
 
* The most detailed and up-to-date documentation is on this wiki.  The [[documentation]] page serves as a general table of contents for these pages.  There is also a list of [[Frequently Asked Questions]].
  
* We have archived material from various [[tutorials]], which provide a more organized overview than the wiki, along with some "how to" information not currently found elsewhere.
+
* The [[Mailing Lists]] archives contain lots of useful information. Please look at the sidebar for mailing list subscription information.
 +
 
 +
* We have archived material from various [[tutorials]], which provide a more organized overview than the wiki, along with some "how to" information not currently found elsewhere. There are also a number of recent workshops outlining ongoing work, such as the full-day [[User_workshop_2015|workshop at ISCA-42]].
  
* A higher-level overview of M5 can be found in our article [http://doi.ieeecomputersociety.org/10.1109/MM.2006.82 ''The M5 Simulator: Modeling Networked Systems''] from the July/Aug 2006 issue of IEEE Micro. If you use M5 in your research, we would appreciate a citation to this paper in any publications you produce.
+
* A higher-level overview of gem5 can be found in our article [http://dx.doi.org/10.1145/2024716.2024718 ''The gem5 Simulator''] from the May 2011 issue of ACM SIGARCH Computer Architecture News. If you use gem5 in your research, we would appreciate a citation to this paper in any publications you produce.
  
* The M5 code is (somewhat sparsely) commented with [http://www.doxygen.org doxygen] comments. You can browse the doxygen-generated documentation [http://www.m5sim.org/docs here].
+
* The gem5 code is (somewhat sparsely) commented with [http://www.doxygen.org doxygen] comments. You can browse the doxygen-generated documentation [http://www.gem5.org/docs here].
  
 
=== Publications ===
 
=== Publications ===
A list of [[publications]] using the M5 simulator is also available. Please append to the list if you publish a paper using M5.
+
A list of [[publications]] using the gem5 simulator is also available. Please append to the list if you publish a paper using gem5.
 +
 
 +
If you use gem5 in your research, we would appreciate a citation to, [http://dx.doi.org/10.1145/2024716.2024718 ''The gem5 Simulator,''] from the May 2011 issue of ACM SIGARCH Computer Architecture News in any publications you produce. In addition, please [[Publications|cite the specific features of gem5]] that you are using as part of your research.
 +
 
  
 
===Acknowledgments===
 
===Acknowledgments===
The M5 simulator is being developed with generous support from several sources, including the National Science Foundation, Hewlett-Packard, Intel, IBM, MIPS, and Sun. Individuals working on M5 have also been supported by an Intel Fellowship (Nate Binkert), a Lucent Fellowship (Lisa Hsu), and a Sloan Research Fellowship (Steve Reinhardt).
+
The gem5 simulator has been developed with generous support from
 +
several sources, including the National Science Foundation, AMD, ARM,
 +
Hewlett-Packard, IBM, Intel, MIPS, and Sun.
 +
Individuals working on gem5 have also been supported by fellowships from
 +
Intel, Lucent, and the Alfred P. Sloan Foundation.
 +
This material is based upon work supported by the National Science
 +
Foundation under the following grants: CCR-0105503, CCR-0219640,
 +
CCR-0324878, EAI/CNS-0205286, and CCR-0105721.
  
This material is based upon work supported by the National Science Foundation under Grant Nos. CCR-0105503 and CCR-0219640. Any opinions, findings and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation (NSF).
+
Any opinions, findings and conclusions or recommendations expressed in
 +
this material are those of the author(s) and do not necessarily
 +
reflect the views of the National Science Foundation (NSF) or any
 +
other sponsor.
  
 
[http://www.m5sim.org/dist/whym5.wav Why is it called M5?]
 
[http://www.m5sim.org/dist/whym5.wav Why is it called M5?]
 
__NOTOC__ __NOEDITSECTION__
 
__NOTOC__ __NOEDITSECTION__

Latest revision as of 23:36, 29 August 2018

The gem5 Simulator
A modular platform for computer-system architecture research

About

  • The gem5 simulator is a modular platform for computer-system architecture research, encompassing system-level architecture as well as processor microarchitecture.

Key features

  • Multiple interchangeable CPU models. gem5 provides four interpretation-based CPU models: a simple one-CPI CPU; a detailed model of an in-order CPU, and a detailed model of an out-of-order CPU. These CPU models use a common high-level ISA description. In addition, gem5 features a KVM-based CPU that uses virtualisation to accelerate simulation.
  • A fully integrated GPU model that executes real machine ISA and supports shared virtual memory with the host CPU.
  • A NoMali GPU model. gem5 comes with an integrated NoMali GPU model that is compatible with the Linux and Android GPU driver stack, and thus removes the need for software rendering. The NoMali GPU does not produce any output, but ensures that CPU-centric experiments produce representative results.
  • Event-driven memory system. gem5 features a detailed, event-driven memory system including caches, crossbars, snoop filters, and a fast and accurate DRAM controller model, for capturing the impact of current and emerging memories, e.g. LPDDR3/4/5, DDR3/4, GDDR5, HBM1/2/3, HMC, WideIO1/2. The components can be arranged flexibly, e.g., to model complex multi-level non-uniform cache hierarchies with heterogeneous memories.
  • A trace-based CPU model that plays back elastic traces, which are dependency and timing annotated traces generated by a probe attached to the out-of-order CPU model. The focus of the Trace CPU model is to achieve memory-system (cache-hierarchy, interconnects and main memory) performance exploration in a fast and reasonably accurate way instead of using the detailed CPU model.
  • Homogeneous and heterogeneous multi-core. The CPU models and caches can be combined in arbitrary topologies, creating homogeneous, and heterogeneous multi-core systems. A MOESI snooping cache coherence protocol keeps the caches coherent.
  • Multiple ISA support. gem5 decouples ISA semantics from its CPU models, enabling effective support of multiple ISAs. Currently gem5 supports the Alpha, ARM, SPARC, MIPS, POWER, RISC-V and x86 ISAs. See Supported Architectures for more information.
  • Full-system capability.
    • Alpha: gem5 models a DEC Tsunami system in sufficient detail to boot unmodified Linux 2.4/2.6, FreeBSD, or L4Ka::Pistachio. We have also booted HP/Compaq's Tru64 5.1 operating system in the past, though we no longer actively maintain that capability.
    • ARM: gem5 can model up to 64 (heterogeneous) cores of a Realview ARM platform, and boot unmodified Linux and Android with a combination of in-order and out-of-order CPUs. The ARM implementation supports 32 or 64-bit kernels and applications.
    • SPARC: The gem5 simulator models a single core of a UltraSPARC T1 processor with sufficient detail to boot Solaris in a similar manner as the Sun T1 Architecture simulator tools (building the hypervisor with specific defines and using the HSMID virtual disk driver).
    • x86: The gem5 simulator supports a standard PC platform
  • Multi-system capability. Multiple systems can be instantiated within a single simulation process. In conjunction with full-system modeling, this feature allows simulation of entire client-server networks.
  • Power and energy modeling. gem5’s objects are arranged in OS-visible power and clock domains, enabling a range of experiments in power- and energy-efficiency. With out-of-the-box support for OS-controller Dynamic Voltage and Frequency (DVFS) scaling, gem5 provides a complete platform for research in future energy-efficient systems. See how to run your own DVFS experiments.
  • Co-simulation with SystemC. gem5 can be included in a SystemC simulation, effectively running as a thread inside the SystemC event kernel, and keeping the events and timelines synchronized between the two worlds. This functionality enables the gem5 components to interoperate with a wide range of System on Chip (SoC) component models, such as interconnects, devices and accelerators. A wrapper for SystemC Transaction Level Modelling (TLM) is provided.

Download

Additional details

  • Application-only support. In application-only (non-full-system) mode, gem5 can execute a variety of architecture/OS binaries with Linux emulation.
  • Platforms. The gem5 simulator runs on most operating systems (Linux, MacOS X, OpenBSD) and architectures (x86, x86-64, ARM, SPARC, Alpha, and PPC). However, all guest platforms aren't supported on all host platforms (most notably Alpha requires little-endian hardware). It is readily portable to other hosts and other Unix-like operating systems that are supported by GCC and/or clang.
  • Licensing. The gem5 simulator is released under a Berkeley-style open source license. Roughly speaking, you are free to use our code however you wish, as long as you leave our copyright on it. For more details, see the LICENSE file included in the source download. Note that the portions of gem5 derived from other sources are also subject to the licensing restrictions of the original sources.

Documentation

There are several sources of documentation for gem5:

  • The Mailing Lists archives contain lots of useful information. Please look at the sidebar for mailing list subscription information.
  • We have archived material from various tutorials, which provide a more organized overview than the wiki, along with some "how to" information not currently found elsewhere. There are also a number of recent workshops outlining ongoing work, such as the full-day workshop at ISCA-42.
  • A higher-level overview of gem5 can be found in our article The gem5 Simulator from the May 2011 issue of ACM SIGARCH Computer Architecture News. If you use gem5 in your research, we would appreciate a citation to this paper in any publications you produce.
  • The gem5 code is (somewhat sparsely) commented with doxygen comments. You can browse the doxygen-generated documentation here.

Publications

A list of publications using the gem5 simulator is also available. Please append to the list if you publish a paper using gem5.

If you use gem5 in your research, we would appreciate a citation to, The gem5 Simulator, from the May 2011 issue of ACM SIGARCH Computer Architecture News in any publications you produce. In addition, please cite the specific features of gem5 that you are using as part of your research.


Acknowledgments

The gem5 simulator has been developed with generous support from several sources, including the National Science Foundation, AMD, ARM, Hewlett-Packard, IBM, Intel, MIPS, and Sun. Individuals working on gem5 have also been supported by fellowships from Intel, Lucent, and the Alfred P. Sloan Foundation. This material is based upon work supported by the National Science Foundation under the following grants: CCR-0105503, CCR-0219640, CCR-0324878, EAI/CNS-0205286, and CCR-0105721.

Any opinions, findings and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation (NSF) or any other sponsor.

Why is it called M5?