Projects

From gem5
Revision as of 03:21, 18 June 2011 by Test (talk | contribs)
Jump to: navigation, search

Below is a list of projects that are based on gem5, are extensions of gem5, or use gem5.

MV5

  • MV5 is a reconfigurable simulator for heterogeneous multicore architectures. It is based on M5v2.0 beta 4.
  • Typical usage: simulating data-parallel applications on SIMT cores that operate over directory-based cache hierarchies. You can also add out-of-order cores to have a heterogeneous system, and all different types of cores can operate under the same address space through the same cache hierarchy.
  • Research projects based on MV5 have been published in ISCA'10, ICCD'09, and IPDPS'10.

Features

  • Single-Instruction, Multiple-Threads (SIMT) cores
  • Directory-based Coherence Cache: MESI/MSI. (Not based on gem)
  • Interconnect: Fully connected and 2D Mesh. (Not based on gem)
  • Threading API/library in system emulation mode (No support for full-system simulation. A benchmark suite using the thread API is provided)

Resources

  • Home Page: [1]
  • Tutorial at ISPASS '11: [2]
  • Google group: [3]