gem5.components.boards.html
gem5.components.boards package¶
Subpackages¶
Submodules¶
- gem5.components.boards.abstract_board module
AbstractBoardAbstractBoard.connect_system_port()AbstractBoard.get_cache_hierarchy()AbstractBoard.get_cache_line_size()AbstractBoard.get_clock_domain()AbstractBoard.get_devices()AbstractBoard.get_dma_ports()AbstractBoard.get_io_bus()AbstractBoard.get_mem_ports()AbstractBoard.get_mem_side_coherent_io_port()AbstractBoard.get_memory()AbstractBoard.get_processor()AbstractBoard.get_workload()AbstractBoard.has_coherent_io()AbstractBoard.has_dma_ports()AbstractBoard.has_io_bus()AbstractBoard.is_fullsystem()AbstractBoard.is_workload_set()AbstractBoard.set_is_workload_set()AbstractBoard.set_mem_mode()AbstractBoard.set_workload()
- gem5.components.boards.abstract_system_board module
- gem5.components.boards.arm_board module
ArmBoardArmBoard.abstractArmBoard.connect_system_port()ArmBoard.createCCObject()ArmBoard.cxx_exportsArmBoard.cxx_extra_basesArmBoard.cxx_param_exportsArmBoard.cxx_template_paramsArmBoard.get_default_kernel_args()ArmBoard.get_disk_device()ArmBoard.get_dma_ports()ArmBoard.get_io_bus()ArmBoard.get_mem_ports()ArmBoard.get_mem_side_coherent_io_port()ArmBoard.has_coherent_io()ArmBoard.has_dma_ports()ArmBoard.has_io_bus()ArmBoard.override_create
- gem5.components.boards.kernel_disk_workload module
- gem5.components.boards.mem_mode module
- gem5.components.boards.riscv_board module
RiscvBoardRiscvBoard.abstractRiscvBoard.cxx_exportsRiscvBoard.cxx_extra_basesRiscvBoard.cxx_param_exportsRiscvBoard.cxx_template_paramsRiscvBoard.generate_device_tree()RiscvBoard.get_default_kernel_args()RiscvBoard.get_disk_device()RiscvBoard.get_dma_ports()RiscvBoard.get_io_bus()RiscvBoard.get_mem_side_coherent_io_port()RiscvBoard.has_coherent_io()RiscvBoard.has_dma_ports()RiscvBoard.has_io_bus()RiscvBoard.override_create
- gem5.components.boards.se_binary_workload module
- gem5.components.boards.simple_board module
SimpleBoardSimpleBoard.abstractSimpleBoard.cxx_exportsSimpleBoard.cxx_extra_basesSimpleBoard.cxx_param_exportsSimpleBoard.cxx_template_paramsSimpleBoard.get_dma_ports()SimpleBoard.get_io_bus()SimpleBoard.get_mem_side_coherent_io_port()SimpleBoard.has_coherent_io()SimpleBoard.has_dma_ports()SimpleBoard.has_io_bus()SimpleBoard.override_create
- gem5.components.boards.test_board module
TestBoardTestBoard.abstractTestBoard.cxx_exportsTestBoard.cxx_extra_basesTestBoard.cxx_param_exportsTestBoard.cxx_template_paramsTestBoard.get_dma_ports()TestBoard.get_io_bus()TestBoard.get_mem_side_coherent_io_port()TestBoard.has_coherent_io()TestBoard.has_dma_ports()TestBoard.has_io_bus()TestBoard.override_create
- gem5.components.boards.x86_board module
X86BoardX86Board.abstractX86Board.cxx_exportsX86Board.cxx_extra_basesX86Board.cxx_param_exportsX86Board.cxx_template_paramsX86Board.get_default_kernel_args()X86Board.get_disk_device()X86Board.get_dma_ports()X86Board.get_io_bus()X86Board.get_mem_side_coherent_io_port()X86Board.has_coherent_io()X86Board.has_dma_ports()X86Board.has_io_bus()X86Board.override_create