gem5.components.cachehierarchies.chi.private_l1_private_l2_cache_hierarchy module

class gem5.components.cachehierarchies.chi.private_l1_private_l2_cache_hierarchy.PrivateL1PrivateL2CacheHierarchy(l1i_size: str, l1i_assoc: int, l1d_size: str, l1d_assoc: int, l2_size: str, l2_assoc: int)

Bases: AbstractRubyCacheHierarchy, AbstractTwoLevelCacheHierarchy

A two level cache hierarchy based on CHI

This hierarchy has a split I/D L1 caches per CPU, a second level of caches (L2) which are private per CPU, a single directory (HNF), and as many memory controllers (SNF) as memory channels. The directory does not have an associated cache.

The network is a simple point-to-point between all of the controllers.

abstract = False

cxx_exports = []

cxx_extra_bases = []

cxx_param_exports = []

cxx_template_params = []

get_coherence_protocol()

Returns the coherence protocol used in the cache hierarchy.

Returns:

The coherence protocol used in the cache hierarchy.

incorporate_cache(board: AbstractBoard) → None

Incorporates the caches into a board.

Each specific hierarchy needs to implement this function and will be unique for each setup.

Parameters:

board – The board in which the cache heirarchy is to be incorporated.

override_create = False