If you use gem5 in your research, we would appreciate a citation to the original paper in any publications you produce. Moreover, we would appreciate if you cite also the speacial features of gem5 which have been developed and contributed to the main line since the publication of the original paper in 2011. In other words, if you use feature X please also cite the according paper Y from the list below.

Original Paper

  • The gem5 Simulator. Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, and David A. Wood. May 2011, ACM SIGARCH Computer Architecture News. doi:10.1145/2024716.2024718.

Special Features of gem5

gem5art and gem5resources


DRAM Controller, DRAM Power Estimation


Elastic Traces

SystemC Coupling

Derivative projects

Below is a list of projects that are based on gem5, are extensions of gem5, or use gem5.


  • Merges 2 popular simulators: gem5 and GPGPU-Sim
  • Simulates CPUs, GPUs, and the interactions between them
  • Models a flexible memory system with support for heterogeneous processors and coherence
  • Supports full-system simulation through GPU driver emulation



  • MV5 is a reconfigurable simulator for heterogeneous multicore architectures. It is based on M5v2.0 beta 4.
  • Typical usage: simulating data-parallel applications on SIMT cores that operate over directory-based cache hierarchies. You can also add out-of-order cores to have a heterogeneous system, and all different types of cores can operate under the same address space through the same cache hierarchy.
  • Research projects based on MV5 have been published in ISCA’10, ICCD’09, and IPDPS’10.


  • Single-Instruction, Multiple-Threads (SIMT) cores
  • Directory-based Coherence Cache: MESI/MSI. (Not based on gems/ruby)
  • Interconnect: Fully connected and 2D Mesh. (Not based on gems/ruby)
  • Threading API/library in system emulation mode (No support for full-system simulation. A benchmark suite using the thread API is provided)


Other Publications related to gem5

Publications using gem5 / m5


  • An Integrated Simulation Tool for Computer Architecture and Cyber-Physical Systems. Hokeun Kim, Armin Wasicek, and Edward A. Lee. In Proceedings of the 6th Workshop on Design, Modeling and Evaluation of Cyber-Physical Systems (CyPhy’17), Seoul, Korea, October 19, 2017. doi:10.1007/978-3-030-17910-6_7. pdf
  • Efficient Programming for Multicore Processor Heterogeneity: OpenMP versus OmpSs. Anastasiia Butko, Florent Bruguier, Abdoulaye Gamatié and Gilles Sassatelli. In Open Source Supercomputing (OpenSuCo’17) Workshop co-located with ISC’17, June 2017. link
  • MAGPIE: System-level Evaluation of Manycore Systems with Emerging Memory Technologies. Thibaud Delobelle, Pierre-Yves Péneau, Abdoulaye Gamatié, Florent Bruguier, Sophiane Senni, Gilles Sassatelli and Lionel Torres, 2nd International Workshop on Emerging Memory Solutions (EMS) co-located with DATE’17, March 2017. link













  • Software Defined Radio - A High Performance Embedded Challenge. H. Lee, Y. Lin, Y. Harel, M. Woh, S. Mahlke, T. Mudge, K. Flautner. Proc. 2005 Int’l Conf. on High Performance Embedded Architectures and Compilers (HiPEAC), November 2005. doi:10.1007/11587514_3. pdf
  • How to Fake 1000 Registers. D. W. Oehmke, N. L. Binkert, S. K. Reinhardt, and T. Mudge. Proc. 38th Ann. Int’l Symp. on Microarchitecture (MICRO), November 2005. doi:10.1109/MICRO.2005.21. pdf
  • Virtualizing Register Context. D. W. Oehmke. Dissertation at the University of Michigan, 2005. pdf
  • Performance Validation of Network-Intensive Workloads on a Full-System Simulator. A. G. Saidi, N. L. Binkert, L. R. Hsu, and S. K. Reinhardt. First Ann. Workshop on Iteraction between Operating System and Computer Architecture (IOSCA), October 2005. pdf
    • An extended version appears as University of Michigan Technical Report CSE-TR-511-05, July 2005. pdf
  • Performance Analysis of System Overheads in TCP/IP Workloads. N. L. Binkert, L. R. Hsu, A. G. Saidi, R. G. Dreslinski, A. L. Schultz, and S. K. Reinhardt. Proc. 14th Int’l Conf. on Parallel Architectures and Compilation Techniques (PACT), September 2005. doi:10.1109/PACT.2005.35. pdf
  • Sampling and Stability in TCP/IP Workloads. L. R. Hsu, A. G. Saidi, N. L. Binkert, and S. K. Reinhardt. Proc. First Annual Workshop on Modeling, Benchmarking, and Simulation (MoBS), June 2005. pdf
  • A Unified Compressed Memory Hierarchy. E. G. Hallnor and S. K. Reinhardt. Proc. 11th Int’l Symp. on High-Performance Computer Architecture (HPCA), February 2005. doi:10.1109/HPCA.2005.4.
  • Analyzing NIC Overheads in Network-Intensive Workloads. N. L. Binkert, L. R. Hsu, A. G. Saidi, R. G. Dreslinski, A. L. Schultz, and S. K. Reinhardt. Eighth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), February 2005.
    • An extended version appears as University of Michigan Technical Report CSE-TR-505-04, December 2004. pdf



  • The Impact of Resource Partitioning on SMT Processors. S. E. Raasch and S. K. Reinhardt. Proc. 12th Int’l Conf. on Parallel Architectures and Compilation Techniques (PACT), pp. 15-25, September 2003. doi:10.1109/PACT.2003.1237998.
  • Network-Oriented Full-System Simulation using M5. N. L. Binkert, E. G. Hallnor, and S. K. Reinhardt. Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), February 2003.
  • Design, Implementation and Use of the MIRV Experimental Compiler for Computer Architecture Research. D. A. Greene. Dissertation at the Universtiy of Michigan, 2003. pdf