If you use gem5 for your research, please cite the following papers.

For your specific case, you can access a list of papers used by your project in the citations.bib file located in the m5out folder, which is generated during the build process of gem5.

  • The gem5 Simulator: Version 20.0+. Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian, Rico Amslinger, Matteo Andreozzi, Adrià Armejach, Nils Asmussen, Brad Beckmann, Srikant Bharadwaj, Gabe Black, Gedare Bloom, Bobby R. Bruce, Daniel Rodrigues Carvalho, Jeronimo Castrillon, Lizhong Chen, Nicolas Derumigny, Stephan Diestelhorst, Wendy Elsasser, Carlos Escuin, Marjan Fariborz, Amin Farmahini-Farahani, Pouya Fotouhi, Ryan Gambord, Jayneel Gandhi, Dibakar Gope, Thomas Grass, Anthony Gutierrez, Bagus Hanindhito, Andreas Hansson, Swapnil Haria, Austin Harris, Timothy Hayes, Adrian Herrera, Matthew Horsnell, Syed Ali Raza Jafri, Radhika Jagtap, Hanhwi Jang, Reiley Jeyapaul, Timothy M. Jones, Matthias Jung, Subash Kannoth, Hamidreza Khaleghzadeh, Yuetsu Kodama, Tushar Krishna, Tommaso Marinelli, Christian Menard, Andrea Mondelli, Miquel Moreto, Tiago Mück, Omar Naji, Krishnendra Nathella, Hoa Nguyen, Nikos Nikoleris, Lena E. Olson, Marc Orr, Binh Pham, Pablo Prieto, Trivikram Reddy, Alec Roelke, Mahyar Samani, Andreas Sandberg, Javier Setoain, Boris Shingarov, Matthew D. Sinclair, Tuan Ta, Rahul Thakur, Giacomo Travaglini, Michael Upton, Nilay Vaish, Ilias Vougioukas, William Wang, Zhengrong Wang, Norbert Wehn, Christian Weis, David A. Wood, Hongil Yoon, Éder F. Zulian. CoRR, 2020. [ arXiv: 2007.03152 ] [ pdf ]

  • The gem5 Simulator. Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, and David A. Wood. ACM SIGARCH Computer Architecture News, May 2011. [ doi: 10.1145/2024716.2024718 ] [ pdf ]

Additionally, we would appreciate it if you could also acknowledge the special features of gem5 that have been developed and contributed to the main line since the publication of the original paper in 2011. In simpler terms, if you use a specific feature X, please cite the corresponding paper Y from the list below.

gem5art and gem5resources


DRAM Controller, DRAM Power Estimation


Elastic Traces

SystemC Coupling

Below is a list of projects that are based on gem5, are extensions of gem5, or use gem5.


  • Merges 2 popular simulators: gem5 and GPGPU-Sim
  • Simulates CPUs, GPUs, and the interactions between them
  • Models a flexible memory system with support for heterogeneous processors and coherence
  • Supports full-system simulation through GPU driver emulation
  • Home Page
  • Overview slides


  • MV5 is a reconfigurable simulator for heterogeneous multicore architectures. It is based on M5v2.0 beta 4.
  • Typical usage: simulating data-parallel applications on SIMT cores that operate over directory-based cache hierarchies. You can also add out-of-order cores to have a heterogeneous system, and all different types of cores can operate under the same address space through the same cache hierarchy.
  • Research projects based on MV5 have been published in ISCA’10, ICCD’09, and IPDPS’10.
  • Features
    • Single-Instruction, Multiple-Threads (SIMT) cores
    • Directory-based Coherence Cache: MESI/MSI. (Not based on gems/ruby)
    • Interconnect: Fully connected and 2D Mesh. (Not based on gems/ruby)
    • Threading API/library in system emulation mode (No support for full-system simulation. A benchmark suite using the thread API is provided)

Please visit Google Scholar page for a list of all papers that use gem5.