gem5.components.cachehierarchies.classic.private_l1_shared_l2_cache_hierarchy module

class gem5.components.cachehierarchies.classic.private_l1_shared_l2_cache_hierarchy.PrivateL1SharedL2CacheHierarchy(l1d_size: str, l1i_size: str, l2_size: str, l1d_assoc: int = 8, l1i_assoc: int = 8, l2_assoc: int = 16, membus: BaseXBar | None = None)

Bases: AbstractClassicCacheHierarchy, AbstractTwoLevelCacheHierarchy

A cache setup where each core has a private L1 Data and Instruction Cache, and a L2 cache is shared with all cores. Table walker ports connect directly to the shared L2 bus by default, ensuring the absence of implicit walk caches unless explicitly requested via a subclass.

abstract = False

cxx_exports = []

cxx_extra_bases = []

cxx_param_exports = []

cxx_template_params = []

get_cpu_side_port() → Port

get_mem_side_port() → Port

incorporate_cache(board: AbstractBoard) → None

Incorporates the caches into a board.

Each specific hierarchy needs to implement this function and will be unique for each setup.

Parameters:

board – The board in which the cache heirarchy is to be incorporated.

override_create = False