gem5.components.memory.dram_interfaces.hbm module

Interfaces for HBM memory devices

These memory “interfaces” contain the timing, energy, etc parameters for each memory type and are usually based on datasheets for the memory devices.

You can use these interfaces in the MemCtrl object as the dram timing interface.

class gem5.components.memory.dram_interfaces.hbm.HBM_1000_4H_1x128(**kwargs)

Bases: DRAMInterface

A single HBM x128 interface (one command and address bus), with default timings based on data publically released (“HBM: Memory Solution for High Performance Processors”, MemCon, 2014), IDD measurement values, and by extrapolating data from other classes.

Architecture values based on published HBM spec.

A 4H stack is defined, 2Gb per die for a total of 1GiB of memory.

IMPORTANT HBM gen1 supports up to 8 128-bit physical channels Configuration defines a single channel, with the capacity set to (full_ stack_capacity / 8) based on 2Gb dies.

To use all 8 channels, set channels parameter to 8 in system configuration.

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
override_create = False
class gem5.components.memory.dram_interfaces.hbm.HBM_1000_4H_1x64(**kwargs)

Bases: HBM_1000_4H_1x128

A single HBM x64 interface (one command and address bus), with default timings based on HBM gen1 and data publically released A 4H stack is defined, 8Gb per die for a total of 4GiB of memory. Note: This defines a pseudo-channel with a unique controller instantiated per pseudo-channel.

Stay at same IO rate (1Gbps) to maintain timing relationship with HBM gen1 class (HBM_1000_4H_x128) where possible.

IMPORTANT For HBM gen2 with pseudo-channel mode, configure 2X channels. Configuration defines a single pseudo channel, with the capacity set to (full_ stack_capacity / 16) based on 8Gb dies. To use all 16 pseudo channels, set channels parameter to 16 in system configuration.

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
override_create = False
class gem5.components.memory.dram_interfaces.hbm.HBM_2000_4H_1x64(**kwargs)

Bases: DRAMInterface

abstract = False
cxx_exports = []
cxx_extra_bases = []
cxx_param_exports = []
cxx_template_params = []
override_create = False