gem5.components.memory.hbm module

HBM2 memory system using HBMCtrl

gem5.components.memory.hbm.HBM2Stack(size: str | None = '4GiB') → AbstractMemorySystem

class gem5.components.memory.hbm.HighBandwidthMemory(dram_interface_class: Type[DRAMInterface], num_channels: int | str, interleaving_size: int | str, size: str | None = None, addr_mapping: str | None = None)

Bases: ChanneledMemory

This class extends ChanneledMemory and can be used to create HBM based memory system where a single physical channel contains two pseudo channels. This is supposed to be used with the HBMCtrl and two dram (HBM2) interfaces per channel.

abstract = False

cxx_exports = []

cxx_extra_bases = []

cxx_param_exports = []

cxx_template_params = []

get_mem_interfaces() → List[AbstractMemory]

Get all memory interfaces in this memory system. Useful when creating physical memory objects.

The “mem interface” is the object that is an AbstractMemory and is used to create the backing store.

get_mem_ports() → Sequence[Tuple[AddrRange, Port]]

Get the ports to connect this memory system to the cache.

override_create = False