gem5-21.0 Released!

Version 21.0 marks one full year of gem5 releases, and on this anniversary, I think we have some of the biggest new features yet! This has been a very productive release with 100 issues, over 813 commits, and 49 unique contributors.

21.0 New features

AMBA CHI protocol implemented in SLICC: Contributed by Tiago Mück

This new protocol provides a single cache controller that can be reused at multiple levels of the cache hierarchy and configured to model multiple instances of MESI and MOESI cache coherency protocols. This implementation is based of Arm’s AMBA 5 CHI specification and provides a scalable framework for the design space exploration of large SoC designs.

See the gem5 documentation for more details. There is also a gem5 blog post on this new protocol as well.

Full support for AMD’s GCN3 GPU model

In previous releases, this model was only partially supported. As of gem5 21.0, this model has been fully integrated and is tested nightly. This model currently only works in syscall emulation mode and requires using the gcn docker container to get the correct version of the ROCm stack. More information can be found in this blog post.

With this full support, we are also providing many applications as well. See gem5-resources for more information.

RISC-V Full system Linux boot support: Contributed by Peter Yuen

The RISC-V model in gem5 can now boot unmodified Linux! Additionally, we have implemented DTB generation and support the Berkeley Boot Loader as the stage 1 boot loader. We have also released a set of resources for you to get started:

New/Changed APIs

There are multiple places where the developers have reduced boilerplate.

See for more details on these two API changes.

Platforms no longer support

Other improvements and new features